X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=fac7b685c225cdcab25739bdadfc44ee2254001d;hb=6f194ad388fedf287a6200ea7efb16c4118ca4c1;hp=f7904c0d3bc6d57ccd2fb52c0c23d1324cd69340;hpb=b48420e3941991b9d3f646e539499327c2417a3c;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index f7904c0..fac7b68 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1,4 +1,4 @@ - +#define DEBUG_FLASH 0 #include #include @@ -49,6 +49,35 @@ #define FLASH_CR_STRT 6 #define FLASH_CR_LOCK 7 + +//32L = 32F1 same CoreID as 32F4! +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) + + +//STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0x38 +#define FLASH_F4_SR_BSY 16 + + void write_uint32(unsigned char* buf, uint32_t ui) { if (!is_bigendian()) { // le -> le (don't swap) buf[0] = ((unsigned char*) &ui)[0]; @@ -92,28 +121,35 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return (*(uint32_t*) sl->q_buf) & 0xff; + return stlink_read_debug32(sl, FLASH_WRPR) & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_WRPR); } static inline uint32_t read_flash_obr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_OBR); } static inline uint32_t read_flash_cr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + uint32_t res; + if(sl->chip_id==STM32F4_CHIP_ID) + res = stlink_read_debug32(sl, FLASH_F4_CR); + else + res = stlink_read_debug32(sl, FLASH_CR); +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return res; } static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + if(sl->chip_id==STM32F4_CHIP_ID) + return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); + else + return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); } static void unlock_flash(stlink_t *sl) { @@ -122,12 +158,15 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ + if(sl->chip_id==STM32F4_CHIP_ID) { + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + } + else { + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); + } - write_uint32(sl->q_buf, FLASH_KEY1); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); - - write_uint32(sl->q_buf, FLASH_KEY2); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); } static int unlock_flash_if(stlink_t *sl) { @@ -145,69 +184,91 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - /* write to 1 only. reset by hw at unlock sequence */ - - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + if(sl->chip_id==STM32F4_CHIP_ID) { + const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); + stlink_write_debug32(sl, FLASH_F4_CR, n); + } + else { + /* write to 1 only. reset by hw at unlock sequence */ + const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); + stlink_write_debug32(sl, FLASH_CR, n); + } } + static void set_flash_cr_pg(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PG; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + if(sl->chip_id==STM32F4_CHIP_ID) { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_CR_PG); + stlink_write_debug32(sl, FLASH_F4_CR, x); + } + else { + const uint32_t n = 1 << FLASH_CR_PG; + stlink_write_debug32(sl, FLASH_CR, n); + } } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + if(sl->chip_id==STM32F4_CHIP_ID) + stlink_write_debug32(sl, FLASH_F4_CR, n); + else + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_per(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_PER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_mer(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_MER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_strt(stlink_t *sl) { - /* assume come on the flash_cr_per path */ - const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + if(sl->chip_id == STM32F4_CHIP_ID) + { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_F4_CR_STRT); + stlink_write_debug32(sl, FLASH_F4_CR, x); + } + else { + /* assume come on the flash_cr_per path */ + const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); + stlink_write_debug32(sl, FLASH_CR, n); + } } static inline uint32_t read_flash_acr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return stlink_read_debug32(sl, FLASH_ACR); } static inline uint32_t read_flash_sr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + uint32_t res; + if(sl->chip_id==STM32F4_CHIP_ID) + res = stlink_read_debug32(sl, FLASH_F4_SR); + else + res = stlink_read_debug32(sl, FLASH_SR); + //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + if(sl->chip_id==STM32F4_CHIP_ID) + return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + else + return read_flash_sr(sl) & (1 << FLASH_SR_BSY); } static void wait_flash_busy(stlink_t *sl) { @@ -222,8 +283,7 @@ static inline unsigned int is_flash_eop(stlink_t *sl) { static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_SR, n); } static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { @@ -233,8 +293,29 @@ static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { } static inline void write_flash_ar(stlink_t *sl, uint32_t n) { - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_AR, n); +} + +static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { + uint32_t x = read_flash_cr(sl); + x &= ~(0x03 << 8); + x |= (n << 8); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, FLASH_F4_CR, x); +} + + +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { + uint32_t x = read_flash_cr(sl); + x &= ~FLASH_F4_CR_SNB_MASK; + x |= (n << FLASH_F4_CR_SNB); + x |= (1 << FLASH_F4_CR_SER); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, FLASH_F4_CR, x); } #if 0 /* todo */ @@ -257,6 +338,7 @@ void stlink_close(stlink_t *sl) { void stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); + stlink_write_debug32(sl, DHCSR, DBGKEY); sl->backend->exit_debug_mode(sl); } @@ -285,10 +367,8 @@ uint32_t stlink_core_id(stlink_t *sl) { return sl->core_id; } -uint16_t stlink_chip_id(stlink_t *sl) { - stlink_read_mem32(sl, 0xE0042000, 4); - uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) | - (sl->q_buf[3] << 24); +uint32_t stlink_chip_id(stlink_t *sl) { + uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); return chip_id; } @@ -298,8 +378,7 @@ uint16_t stlink_chip_id(stlink_t *sl) { * @param cpuid pointer to the result object */ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - stlink_read_mem32(sl, CM3_REG_CPUID, 4); - uint32_t raw = read_uint32(sl->q_buf, 0); + uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; @@ -314,8 +393,16 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { */ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); - chip_params_t *params = NULL; + const chip_params_t *params = NULL; + + sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); + + /* Fix chip_id for F4 rev A errata */ + if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) { + chip_id = 0x413; + } + sl->chip_id = chip_id; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == (chip_id & 0xFFF)) { @@ -335,9 +422,10 @@ int stlink_load_device_params(stlink_t *sl) { // read flash size from hardware, if possible... if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) { + sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else { - stlink_read_mem32(sl, params->flash_size_reg, 4); - uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; } sl->flash_pgsz = params->flash_pagesize; @@ -345,9 +433,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; - sl->core_id = stlink_core_id(sl); - - ILOG("Device connected is: %s\n", params->description); + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); + // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, sl->flash_pgsz); @@ -359,6 +446,11 @@ void stlink_reset(stlink_t *sl) { sl->backend->reset(sl); } +void stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset ***\n"); + sl->backend->jtag_reset(sl, value); +} + void stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); sl->backend->run(sl); @@ -413,6 +505,17 @@ void stlink_version(stlink_t *sl) { } } +uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { + uint32_t data = sl->backend->read_debug32(sl, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + return data; +} + +void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); + sl->backend->write_debug32(sl, addr, data); +} + void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { @@ -547,7 +650,7 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < 2) + if (sl->q_len <= 0 || sl->verbose < UDEBUG) return; if (sl->verbose > 2) fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len); @@ -700,6 +803,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; + int num_zero = 0; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -711,6 +815,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) for (off = 0; off < size; off += 1024) { size_t read_size = 1024; size_t rounded_size; + size_t index; if ((off + read_size) > size) read_size = size - off; @@ -721,12 +826,21 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + off, rounded_size); + for(index = 0; index < read_size; index ++) { + if (sl->q_buf[index] == 0) + num_zero ++; + else + num_zero = 0; + } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); goto on_error; } } + /* Ignore NULL Bytes at end of file */ + ftruncate(fd, size - num_zero); + /* success */ error = 0; @@ -743,40 +857,75 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s return 0; } +uint32_t calculate_F4_sectornum(uint32_t flashaddr){ + flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + if (flashaddr<0x4000) return (0); + else if(flashaddr<0x8000) return(1); + else if(flashaddr<0xc000) return(2); + else if(flashaddr<0x10000) return(3); + else if(flashaddr<0x20000) return(4); + else return(flashaddr/0x20000)+4; + +} + +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ + if(sl->chip_id == STM32F4_CHIP_ID) { + uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; + } + return (sl->flash_pgsz); +} + /** * Erase a page of flash, assumes sl is fully populated with things like chip/core ids * @param sl stlink context - * @param page + * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - /* page an addr in the page to erase */ - ILOG("Erasing flash page at addr: %#x\n", page); - if (sl->core_id == STM32L_CORE_ID) + ILOG("Erasing flash page at addr: %#x\n", flashaddr); + if (sl->chip_id == STM32F4_CHIP_ID) + { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* select the page to erase */ + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); + + /* start erase operation */ + set_flash_cr_strt(sl); + + /* wait for completion */ + wait_flash_busy(sl); + + /* relock the flash */ + //todo: fails to program if this is in + lock_flash(sl); +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); +#endif + } + else if (sl->core_id == STM32L_CORE_ID) { -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) uint32_t val; /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); @@ -784,14 +933,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) } /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); @@ -800,14 +946,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* unused: unlock the option byte block */ #if 0 - write_uint32(sl->q_buf, 0xfbead9c8); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x24252627); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); /* check pecr.optlock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 2)) { fprintf(stderr, "pecr.prglock not clear\n"); @@ -817,25 +960,37 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* set pecr.{erase,prog} */ val |= (1 << 9) | (1 << 3); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - /* wait for sr.busy to be cleared */ - while (1) +#if 0 /* fix_to_be_confirmed */ + + /* wait for sr.busy to be cleared + MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + wrong and we do not need to wait here for clearing the busy bit. + TEXANE: ok, if experience says so and it works for you, we comment + it. If someone has a problem, please drop an email. + */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; } +#endif /* fix_to_be_confirmed */ + /* write 0 to the first word of the page to be erased */ - memset(sl->q_buf, 0, sizeof(uint32_t)); - stlink_write_mem32(sl, page, sizeof(uint32_t)); + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + { + } /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID) { @@ -849,7 +1004,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) set_flash_cr_per(sl); /* select the page to erase */ - write_flash_ar(sl, page); + write_flash_ar(sl, flashaddr); /* start erase operation, reset by hw with bsy bit */ set_flash_cr_strt(sl); @@ -860,6 +1015,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* relock the flash */ lock_flash(sl); } + else { WLOG("unknown coreid: %x\n", sl->core_id); return -1; @@ -998,6 +1154,44 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return res; } +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { + size_t off; + if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); + return 0; + } + ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += sl->flash_pgsz) { + size_t aligned_size; + + /* adjust last page size */ + size_t cmp_size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > length) + cmp_size = length - off; + + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); + + stlink_read_mem32(sl, address + off, aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + WLOG("Verification of flash failed at offset: %zd\n", off); + return -1; + } + } + ILOG("Flash written and verified! jolly good!\n"); + return 0; + +} int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; @@ -1005,6 +1199,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); /* check addr range is inside the flash */ + stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; @@ -1026,7 +1221,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned stlink_core_id(sl); /* erase each page */ int page_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); @@ -1037,123 +1232,147 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if (sl->core_id == STM32L_CORE_ID) - { - /* use fast word write. todo: half page. */ + if (sl->chip_id == STM32F4_CHIP_ID) { + /* todo: check write operation */ - uint32_t val; + /* First unlock the cr */ + unlock_flash_if(sl); -#if 0 /* todo: check write operation */ + /* set parallelisim to 32 bit*/ + write_flash_cr_psiz(sl, 2); - uint32_t nwrites = sl->flash_pgsz; + /* set programming mode */ + set_flash_cr_pg(sl); - redo_write: +#define PROGRESS_CHUNK_SIZE 0x1000 + /* write a word in program memory */ + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + if (sl->verbose >= 1) { + if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; + const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE; + fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); + } + } -#endif /* todo: check write operation */ + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); - /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - - /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); - if (val & (1 << 0)) - { - fprintf(stderr, "pecr.pelock not clear\n"); - return -1; - } + /* wait for sr.busy to be cleared */ + wait_flash_busy(sl); - /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - - /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); - if (val & (1 << 1)) - { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } + } + /* Relock flash */ + lock_flash(sl); - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) - { - if (sl->verbose >= 1) - { - if ((off & (sl->flash_pgsz - 1)) == 0) - { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = off / sl->flash_pgsz; - const uint32_t pgcount = len / sl->flash_pgsz; - fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount); - } - } +#if 0 /* todo: debug mode */ + fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); +#endif - memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t)); - stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); - /* wait for sr.busy to be cleared */ - while (1) - { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; - } -#if 0 /* todo: check redo write operation */ + } //STM32F4END - /* check written bytes. todo: should be on a per page basis. */ - stlink_read_mem32(sl, addr + off, sizeof(uint32_t)); - if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) - { - /* re erase the page and redo the write operation */ - uint32_t page; - uint32_t val; + else if (sl->core_id == STM32L_CORE_ID) { + /* use fast word write. todo: half page. */ + uint32_t val; - /* fail if successive write count too low */ - if (nwrites < sl->flash_pgsz) { - fprintf(stderr, "writes operation failure count too high, aborting\n"); - return -1; - } +#if 0 /* todo: check write operation */ - nwrites = 0; + uint32_t nwrites = sl->flash_pgsz; - /* assume addr aligned */ - if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); - page = addr + off; + redo_write: - fprintf(stderr, "invalid write @%x(%x): %x != %x. retrying.\n", - page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); +#endif /* todo: check write operation */ - /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + /* disable pecr protection */ + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 0)) { + fprintf(stderr, "pecr.pelock not clear\n"); + return -1; + } + + /* unlock program memory */ + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 1)) { + fprintf(stderr, "pecr.prglock not clear\n"); + return -1; + } + + /* write a word in program memory */ + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + if (sl->verbose >= 1) { + if ((off & (sl->flash_pgsz - 1)) == 0) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + const uint32_t pgnum = off / sl->flash_pgsz; + const uint32_t pgcount = len / sl->flash_pgsz; + fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount); + } + } + + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); + + /* wait for sr.busy to be cleared */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { + } - stlink_erase_flash_page(sl, page); +#if 0 /* todo: check redo write operation */ - goto redo_write; - } + /* check written bytes. todo: should be on a per page basis. */ + data = stlink_read_debug32(sl, addr + off); + if (data == *(uint32_t*)(base + off)) { + /* re erase the page and redo the write operation */ + uint32_t page; + uint32_t val; - /* increment successive writes counter */ - ++nwrites; + /* fail if successive write count too low */ + if (nwrites < sl->flash_pgsz) { + fprintf(stderr, "writes operation failure count too high, aborting\n"); + return -1; + } -#endif /* todo: check redo write operation */ + nwrites = 0; - } + /* assume addr aligned */ + if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); + page = addr + off; + + fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", + page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); + + /* reset lock bits */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + + stlink_erase_flash_page(sl, page); + + goto redo_write; + } - /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + /* increment successive writes counter */ + ++nwrites; + +#endif /* todo: check redo write operation */ + } + /* reset lock bits */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID) { ILOG("Starting Flash write for VL core id\n"); /* flash loader initialization */ @@ -1187,27 +1406,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } - - ILOG("Starting verification of write complete\n"); - for (off = 0; off < len; off += sl->flash_pgsz) { - size_t aligned_size; - - /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) - cmp_size = len - off; - - aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - - stlink_read_mem32(sl, addr + off, aligned_size); - - if (memcmp(sl->q_buf, base + off, cmp_size)) - return -1; - } - ILOG("Flash written and verified! jolly good!\n"); - return 0; + + return stlink_verify_write_flash(sl, addr, base, len); } /** @@ -1266,7 +1466,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; } @@ -1298,7 +1498,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; }