X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=dc24161d84845438153f0102065114bf03d650db;hb=7fbd79eef39af26ba53d8117b8f80fc70b07ebd5;hp=a86d9854926ecf6928264187538f9ef7b08e618e;hpb=fde8b6b24e8c3b9201195c78663a40f05fa93d1e;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index a86d985..dc24161 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -14,16 +14,15 @@ #include "stlink-common.h" #include "uglylogging.h" -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) +#ifndef _WIN32 +#define O_BINARY 0 +#endif /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -35,6 +34,7 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab @@ -63,6 +63,47 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + ((1lu< le (don't swap) @@ -134,23 +177,33 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { } static inline uint32_t read_flash_cr(stlink_t *sl) { - uint32_t res; - if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4)) - res = stlink_read_debug32(sl, FLASH_F4_CR); - else - res = stlink_read_debug32(sl, FLASH_CR); + uint32_t res; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + res = stlink_read_debug32(sl, FLASH_F4_CR); + else if (sl->chip_id == STM32_CHIPID_L4) + res = stlink_read_debug32(sl, STM32L4_FLASH_CR); + else + res = stlink_read_debug32(sl, FLASH_CR); #if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); + fprintf(stdout, "CR:0x%x\n", res); #endif - return res; + return res; } static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); - else - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + uint32_t cr = read_flash_cr(sl); + + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + return cr & (1 << FLASH_F4_CR_LOCK); + else if (sl->chip_id == STM32_CHIPID_L4) + return cr & (1lu << STM32L4_FLASH_CR_LOCK); + else + return cr & (1 << FLASH_CR_LOCK); } static void unlock_flash(stlink_t *sl) { @@ -158,15 +211,19 @@ static void unlock_flash(stlink_t *sl) { 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. - */ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + */ + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + } else if (sl->chip_id == STM32_CHIPID_L4) { + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2); + } else { + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); } - else { - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); - } } @@ -185,11 +242,15 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - stlink_write_debug32(sl, FLASH_F4_CR, n); - } - else { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); + stlink_write_debug32(sl, FLASH_F4_CR, n); + } else if (sl->chip_id == STM32_CHIPID_L4) { + const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK); + stlink_write_debug32(sl, STM32L4_FLASH_CR, n); + } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); stlink_write_debug32(sl, FLASH_CR, n); @@ -198,12 +259,18 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_CR_PG); - stlink_write_debug32(sl, FLASH_F4_CR, x); - } - else { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_CR_PG); + stlink_write_debug32(sl, FLASH_F4_CR, x); + } else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + } else { const uint32_t n = 1 << FLASH_CR_PG; stlink_write_debug32(sl, FLASH_CR, n); } @@ -211,8 +278,10 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - stlink_write_debug32(sl, FLASH_F4_CR, n); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); } @@ -228,35 +297,47 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else + stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); + else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR); + x &=~ STM32L4_FLASH_CR_OPBITS; + x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + } else stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); - else + stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); + else stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); } static void set_flash_cr_strt(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, x); - } - else { - stlink_write_debug32( - sl, FLASH_CR, - stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) ); - } + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_F4_CR_STRT); + stlink_write_debug32(sl, FLASH_F4_CR, x); + } else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = read_flash_cr(sl); + x |= (1lu << STM32L4_FLASH_CR_STRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + } else { + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + } } static inline uint32_t read_flash_acr(stlink_t *sl) { @@ -264,20 +345,28 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { } static inline uint32_t read_flash_sr(stlink_t *sl) { - uint32_t res; - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - res = stlink_read_debug32(sl, FLASH_F4_SR); - else - res = stlink_read_debug32(sl, FLASH_SR); + uint32_t res; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + res = stlink_read_debug32(sl, FLASH_F4_SR); + else if (sl->chip_id == STM32_CHIPID_L4) + res = stlink_read_debug32(sl, STM32L4_FLASH_SR); + else + res = stlink_read_debug32(sl, FLASH_SR); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); - else - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + else if (sl->chip_id == STM32_CHIPID_L4) + return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); + else + return read_flash_sr(sl) & (1 << FLASH_SR_BSY); } static void wait_flash_busy(stlink_t *sl) { @@ -290,8 +379,7 @@ static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; fprintf(stdout, "Mass erasing"); fflush(stdout); - while (is_flash_busy(sl)) - { + while (is_flash_busy(sl)) { usleep(10000); i++; if (i % 100 == 0) { @@ -343,15 +431,17 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_F4_CR, x); } -#if 0 /* todo */ - -static void disable_flash_read_protection(stlink_t *sl) { - /* erase the option byte area */ - /* rdp = 0x00a5; */ - /* reset */ +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_OPBITS; + x &=~ STM32L4_FLASH_CR_PAGEMASK; + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } -#endif /* todo */ - // Delegates to the backends... @@ -422,16 +512,17 @@ int stlink_load_device_params(stlink_t *sl) { const chip_params_t *params = NULL; sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); - + uint32_t flash_size; + sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); - if((cpuid & 0xfff0) == 0xc240) + if ((cpuid & 0xfff0) == 0xc240) sl->chip_id = 0x413; } - for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == sl->chip_id) { params = &devices[i]; break; @@ -441,30 +532,45 @@ int stlink_load_device_params(stlink_t *sl) { WLOG("unknown chip id! %#x\n", chip_id); return -1; } - + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - - // read flash size from hardware, if possible... - if (sl->chip_id == STM32_CHIPID_F2) { - sl->flash_size = 0x100000; /* Use maximum, User must care!*/ - } else if (sl->chip_id == STM32_CHIPID_F4) { - sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID + flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3); + if (params->flash_size_reg & 2) + flash_size = flash_size >>16; + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { + // 0 is 384k and 1 is 256k + if ( flash_size == 0 ) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } } else { - uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; } sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; - + + //medium and low devices have the same chipid. ram size depends on flash size. + //STM32F100xx datasheet Doc ID 16455 Table 2 + if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + sl->sram_size = 0x1000; + } + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - sl->flash_pgsz); + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); return 0; } @@ -518,7 +624,7 @@ void stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); sl->backend->version(sl); _parse_version(sl, &sl->version); - + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); DLOG("stlink version = 0x%x\n", sl->version.stlink_v); @@ -532,6 +638,22 @@ void stlink_version(stlink_t *sl) { } } +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); + if (voltage != -1) { + DLOG("target voltage = %ldmV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } + } else { + DLOG("reading voltage not supported by backend\n"); + } + return voltage; +} + uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { uint32_t data = sl->backend->read_debug32(sl, addr); DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); @@ -547,7 +669,7 @@ void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return; + abort(); } sl->backend->write_mem32(sl, addr, len); } @@ -557,7 +679,7 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return; + abort(); } sl->backend->read_mem32(sl, addr, len); } @@ -567,7 +689,7 @@ void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); - return; + abort(); } sl->backend->write_mem8(sl, addr, len); } @@ -655,15 +777,15 @@ void stlink_step(stlink_t *sl) { int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return mode; - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return mode; - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return mode; + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return mode; + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return mode; + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return mode; } DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; @@ -714,17 +836,17 @@ void stlink_core_stat(stlink_t *sl) { return; switch (sl->q_buf[0]) { - case STLINK_CORE_RUNNING: - sl->core_stat = STLINK_CORE_RUNNING; - DLOG(" core status: running\n"); - return; - case STLINK_CORE_HALTED: - sl->core_stat = STLINK_CORE_HALTED; - DLOG(" core status: halted\n"); - return; - default: - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - fprintf(stderr, " core status: unknown\n"); + case STLINK_CORE_RUNNING: + sl->core_stat = STLINK_CORE_RUNNING; + DLOG(" core status: running\n"); + return; + case STLINK_CORE_HALTED: + sl->core_stat = STLINK_CORE_HALTED; + DLOG(" core status: halted\n"); + return; + default: + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + fprintf(stderr, " core status: unknown\n"); } } @@ -737,11 +859,11 @@ void stlink_print_data(stlink_t * sl) { for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { /* - if (sl->q_data_dir == Q_DATA_OUT) - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - else - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - */ + if (sl->q_data_dir == Q_DATA_OUT) + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + else + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + */ } fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]); } @@ -761,7 +883,7 @@ static int map_file(mapped_file_t* mf, const char* path) { int error = -1; struct stat st; - const int fd = open(path, O_RDONLY); + const int fd = open(path, O_RDONLY | O_BINARY); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); return -1; @@ -831,8 +953,10 @@ int stlink_fwrite_sram int error = -1; size_t off; + size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + if (map_file(&mf, path) == -1) { fprintf(stderr, "map_file() == -1\n"); return -1; @@ -848,17 +972,23 @@ int stlink_fwrite_sram } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { fprintf(stderr, "addr too high\n"); goto on_error; - } else if ((addr & 3) || (mf.len & 3)) { + } else if (addr & 3) { /* todo */ - fprintf(stderr, "unaligned addr or size\n"); + fprintf(stderr, "unaligned addr\n"); goto on_error; } + len = mf.len; + + if(len & 3) { + len -= len & 3; + } + /* do the copy by 1k blocks */ - for (off = 0; off < mf.len; off += 1024) { + for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > mf.len) - size = mf.len - off; + if ((off + size) > len) + size = len - off; memcpy(sl->q_buf, mf.base + off, size); @@ -869,6 +999,11 @@ int stlink_fwrite_sram stlink_write_mem32(sl, addr + off, size); } + if(mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + len, mf.len - len); + } + /* check the file ha been written */ if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); @@ -894,7 +1029,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -903,32 +1040,32 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } if (size <1) - size = sl->flash_size; + size = sl->flash_size; if (size > sl->flash_size) - size = sl->flash_size; + size = sl->flash_size; /* do the copy by 1k blocks */ for (off = 0; off < size; off += 1024) { size_t read_size = 1024; - size_t rounded_size; - size_t index; + size_t rounded_size; + size_t index; if ((off + read_size) > size) - read_size = size - off; + read_size = size - off; /* round size if needed */ - rounded_size = read_size; + rounded_size = read_size; if (rounded_size & 3) - rounded_size = (rounded_size + 4) & ~(3); + rounded_size = (rounded_size + 4) & ~(3); stlink_read_mem32(sl, addr + off, rounded_size); - for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; - } + for(index = 0; index < read_size; index ++) { + if (sl->q_buf[index] == erased_pattern) + num_empty ++; + else + num_empty = 0; + } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); goto on_error; @@ -936,7 +1073,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } /* Ignore NULL Bytes at end of file */ - ftruncate(fd, size - num_empty); + if (!ftruncate(fd, size - num_empty)) { + error = -1; + } /* success */ error = 0; @@ -963,24 +1102,51 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s } uint32_t calculate_F4_sectornum(uint32_t flashaddr){ + uint32_t offset = 0; flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x4000) return (0); - else if(flashaddr<0x8000) return(1); - else if(flashaddr<0xc000) return(2); - else if(flashaddr<0x10000) return(3); - else if(flashaddr<0x20000) return(4); - else return(flashaddr/0x20000)+4; - + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + if (flashaddr<0x4000) return (offset + 0); + else if(flashaddr<0x8000) return(offset + 1); + else if(flashaddr<0xc000) return(offset + 2); + else if(flashaddr<0x10000) return(offset + 3); + else if(flashaddr<0x20000) return(offset + 4); + else return offset + (flashaddr/0x20000) +4; + +} + +// Returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR); + flashaddr -= STM32_FLASH_BASE; + if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = sl->flash_size / 2; + if (flashaddr > banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return bker | flashaddr/sl->flash_pgsz; } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { - uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector<4) sl->flash_pgsz=0x4000; - else if(sector<5) sl->flash_pgsz=0x10000; - else sl->flash_pgsz=0x20000; - } - return (sl->flash_pgsz); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sector>= 12) { + sector -= 12; + } + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; + } + return (sl->flash_pgsz); } /** @@ -991,182 +1157,187 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* select the page to erase */ - // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* select the page to erase */ + if (sl->chip_id == STM32_CHIPID_L4) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + write_flash_cr_bker_pnb(sl, page); + } else { + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... + if (sector >= 12) sector += 4; - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector); + } - /* start erase operation */ - set_flash_cr_strt(sl); + /* start erase operation */ + set_flash_cr_strt(sl); - /* wait for completion */ - wait_flash_busy(sl); + /* wait for completion */ + wait_flash_busy(sl); - /* relock the flash */ - //todo: fails to program if this is in - lock_flash(sl); + /* relock the flash */ + //todo: fails to program if this is in + lock_flash(sl); #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) - { - - uint32_t val; - - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); - - /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) - { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) - { - WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; - } + /* check if the locks are set */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + if((val & (1<<0))||(val & (1<<1))) { + /* disable pecr protection */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); + + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } - /* unused: unlock the option byte block */ -#if 0 - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); - - /* check pecr.optlock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 2)) - { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } -#endif + /* unlock program memory */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); - /* set pecr.{erase,prog} */ - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return -1; + } + } + /* set pecr.{erase,prog} */ + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); #if 0 /* fix_to_be_confirmed */ - /* wait for sr.busy to be cleared - MP: Test shows that busy bit is not set here. Perhaps, PM0062 is - wrong and we do not need to wait here for clearing the busy bit. - TEXANE: ok, if experience says so and it works for you, we comment - it. If someone has a problem, please drop an email. - */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - { - } + /* wait for sr.busy to be cleared + * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + * wrong and we do not need to wait here for clearing the busy bit. + * TEXANE: ok, if experience says so and it works for you, we comment + * it. If someone has a problem, please drop an email. + */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + ; #endif /* fix_to_be_confirmed */ - /* write 0 to the first word of the page to be erased */ - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing - page erase command, even though PM0062 recommends to wait before it. - Test shows that a few iterations is performed in the following loop - before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - { + /* write 0 to the first word of the page to be erased */ + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) + ; + + /* reset lock bits */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->core_id == STM32VL_CORE_ID + || sl->core_id == STM32F0_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F303_HIGH + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* set the page erase bit */ + set_flash_cr_per(sl); + + /* select the page to erase */ + write_flash_ar(sl, flashaddr); + + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); + + /* wait for completion */ + wait_flash_busy(sl); + + /* relock the flash */ + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return -1; } - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } - else if (sl->core_id == STM32VL_CORE_ID) - { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set the page erase bit */ - set_flash_cr_per(sl); + /* todo: verify the erased page */ - /* select the page to erase */ - write_flash_ar(sl, flashaddr); + return 0; +} - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); +int stlink_erase_flash_mass(stlink_t *sl) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + /* erase each page */ + int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + /* addr must be an addr inside the page */ + stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + return -1; + } + fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fflush(stdout); + } + fprintf(stdout, "\n"); + } else { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); - /* wait for completion */ - wait_flash_busy(sl); + /* unlock if locked */ + unlock_flash_if(sl); - /* relock the flash */ - lock_flash(sl); - } + /* set the mass erase bit */ + set_flash_cr_mer(sl); - else { - WLOG("unknown coreid: %x\n", sl->core_id); - return -1; - } + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); - /* todo: verify the erased page */ + /* wait for completion */ + wait_flash_busy_progress(sl); - return 0; -} + /* relock the flash */ + lock_flash(sl); -int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { - /* erase each page */ - int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; - for (i = 0; i < num_pages; i++) { - /* addr must be an addr inside the page */ - stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); - return -1; - } - fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); - fflush(stdout); - } - fprintf(stdout, "\n"); - } - else { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy_progress(sl); - - /* relock the flash */ - lock_flash(sl); - - /* todo: verify the erased memory */ - } + /* todo: verify the erased memory */ + } return 0; } @@ -1208,71 +1379,220 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ }; + /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ + static const uint8_t loader_code_stm32f0[] = { +#if 1 + /* + * These two NOPs here are a safety precaution, added by Pekka Nikander + * while debugging the STM32F05x support. They may not be needed, but + * there were strange problems with simpler programs, like a program + * that had just a breakpoint or a program that first moved zero to register r2 + * and then had a breakpoint. So, it appears safest to have these two nops. + * + * Feel free to remove them, if you dare, but then please do test the result + * rigorously. Also, if you remove these, it may be a good idea first to + * #if 0 them out, with a comment when these were taken out, and to remove + * these only a few months later... But YMMV. + */ + 0x00, 0x30, // nop /* add r0,#0 */ + 0x00, 0x30, // nop /* add r0,#0 */ +#endif + 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE + 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ + 0x04, 0x26, // mov r6, #4 /* PGERR */ + // write_half_word: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0x2B, 0x43, // orr r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ + 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ + 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ + // busy: + 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ + 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ + 0xFC, 0xD0, // beq busy + + 0x33, 0x42, // tst r3, r6 /* PGERR */ + 0x04, 0xD1, // bne exit + + 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */ + 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */ + 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ + 0x00, 0x2A, // cmp r2, #0 + 0xF0, 0xD1, // bne write_half_word + // exit: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0xAB, 0x43, // bic r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ + 0x00, 0xBE, // bkpt #0x00 + 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + }; + static const uint8_t loader_code_stm32l[] = { - /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr - r2, input, word count - r3, output, word count - */ + /* openocd.git/contrib/loaders/flash/stm32lx.S + r0, input, dest addr + r1, input, source addr + r2, input, word count + r3, output, word count + */ + + 0x00, 0x23, + 0x04, 0xe0, + + 0x51, 0xf8, 0x04, 0xcb, + 0x40, 0xf8, 0x04, 0xcb, + 0x01, 0x33, + + 0x93, 0x42, + 0xf8, 0xd3, + 0x00, 0xbe + }; + + static const uint8_t loader_code_stm32l0[] = { + + /* + r0, input, dest addr + r1, input, source addr + r2, input, word count + r3, output, word count + */ - 0x00, 0x23, - 0x04, 0xe0, + 0x00, 0x23, + 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x0c, 0x68, + 0x04, 0x60, + 0x01, 0x33, + 0x04, 0x31, + 0x04, 0x30, - 0x93, 0x42, - 0xf8, 0xd3, - 0x00, 0xbe + 0x93, 0x42, + 0xf8, 0xd3, + 0x00, 0xbe }; - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s - 0x07, 0x4b, + 0x07, 0x4b, - 0x62, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, + 0x62, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, - 0x00, 0xbe, + 0x00, 0xbe, - 0x00, 0x3c, 0x02, 0x40, - }; + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0x92, 0x00, + + 0x08, 0x4b, + 0x62, 0xb1, + 0x04, 0x78, + 0x0c, 0x70, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x01, 0x00, + 0x01, 0xf1, 0x01, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + 0x00, 0xbf, + + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0x08, 0x4b, // start: ldr r3, [pc, #32] ; + 0x72, 0xb1, // next: cbz r2, + 0x04, 0x68, // ldr r4, [r0, #0] + 0x45, 0x68, // ldr r5, [r0, #4] + 0x0c, 0x60, // str r4, [r1, #0] + 0x4d, 0x60, // str r5, [r1, #4] + 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n + 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 + 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 + 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xef, 0xe7, // b.n + 0x00, 0xbe, // done: bkpt 0x0000 + 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + }; + + static const uint8_t loader_code_stm32f7[] = { + 0x08, 0x4b, + 0x72, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xef, 0xe7, + 0x00, 0xbe, // bkpt #0x00 + 0x00, 0x3c, 0x02, 0x40, + }; const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */ - { - loader_code = loader_code_stm32l; - loader_size = sizeof(loader_code_stm32l); - } - else if (sl->core_id == STM32VL_CORE_ID) - { - loader_code = loader_code_stm32vl; - loader_size = sizeof(loader_code_stm32vl); - } - else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) - { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } - else - { - WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); - return -1; + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ + loader_code = loader_code_stm32l; + loader_size = sizeof(loader_code_stm32l); + } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F303_HIGH + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { + loader_code = loader_code_stm32vl; + loader_size = sizeof(loader_code_stm32vl); + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)){ + int voltage = stlink_target_voltage(sl); + if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } + } else if (sl->chip_id == STM32_CHIPID_F7){ + loader_code = loader_code_stm32f7; + loader_size = sizeof(loader_code_stm32f7); + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { + loader_code = loader_code_stm32f0; + loader_size = sizeof(loader_code_stm32f0); + } else if (sl->chip_id == STM32_CHIPID_L0) { + loader_code = loader_code_stm32l0; + loader_size = sizeof(loader_code_stm32l0); + } else if (sl->chip_id == STM32_CHIPID_L4) { + loader_code = loader_code_stm32l4; + loader_size = sizeof(loader_code_stm32l4); + } else { + ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); + return -1; } memcpy(sl->q_buf, loader_code, loader_size); @@ -1327,7 +1647,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - WLOG("Verification of flash failed at offset: %zd\n", off); + ELOG("Verification of flash failed at offset: %zd\n", off); return -1; } } @@ -1336,12 +1656,20 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) -{ +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) +{ unsigned int count; + unsigned int num_half_pages = len / pagesize; uint32_t val; + uint32_t flash_regs_base; flash_loader_t fl; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + ILOG("Starting Half page flash write for STM32L core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1349,21 +1677,20 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns return -1; } /* Unlock already done */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {} -#define L1_WRITE_BLOCK_SIZE 0x80 for (count = 0; count < num_half_pages; count ++) { - if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) { - WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return -1; } /* wait for sr.busy to be cleared */ @@ -1373,40 +1700,43 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) { } } - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~(1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", - len, len, addr, addr); + len, len, addr, addr); /* check addr range is inside the flash */ stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { - WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; } else if ((addr + len) < addr) { - WLOG("addr overruns\n"); + ELOG("addr overruns\n"); return -1; } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - WLOG("addr too high\n"); + ELOG("addr too high\n"); return -1; - } else if ((addr & 1) || (len & 1)) { - WLOG("unaligned addr or size\n"); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); return -1; + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - WLOG("addr not a multiple of pagesize, not supported\n"); + ELOG("addr not a multiple of pagesize, not supported\n"); return -1; } @@ -1417,197 +1747,166 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", - (unsigned long)addr + off); + (unsigned long)addr + off); fflush(stdout); page_count++; } fprintf(stdout,"\n"); - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); - - if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { - /* todo: check write operation */ - - ILOG("Starting Flash write for F2/F4\n"); - /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); - return -1; - } - - /* First unlock the cr */ - unlock_flash_if(sl); - - /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - /* set parallelisim to 32 bit*/ - write_flash_cr_psiz(sl, 2); - - /* set programming mode */ - set_flash_cr_pg(sl); - - for(off = 0; off < len;) { - size_t size = len - off > 0x8000 ? 0x8000 : len - off; - - printf("size: %u\n", size); - - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); - return -1; - } - - off += size; - } - -#if 0 -#define PROGRESS_CHUNK_SIZE 0x1000 - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (sl->verbose >= 1) { - if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; - const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; - fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); - } - } - - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - - /* wait for sr.busy to be cleared */ - wait_flash_busy(sl); - - } -#endif - /* Relock flash */ - lock_flash(sl); + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); + + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F7) || + (sl->chip_id == STM32_CHIPID_L4)) { + /* todo: check write operation */ + + ILOG("Starting Flash write for F2/F4/L4\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + ELOG("init_flash_loader() == -1\n"); + return -1; + } -#if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); -#endif + /* First unlock the cr */ + unlock_flash_if(sl); + + /* TODO: Check that Voltage range is 2.7 - 3.6 V */ + if (sl->chip_id != STM32_CHIPID_L4) { + /* set parallelisim to 32 bit*/ + int voltage = stlink_target_voltage(sl); + if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } + } else { + /* L4 does not have a byte-write mode */ + int voltage = stlink_target_voltage(sl); + if (voltage <= 2700) { + printf("Target voltage (%d mV) too low for flash writes!\n", voltage); + return -1; + } + } + /* set programming mode */ + set_flash_cr_pg(sl); + for(off = 0; off < len;) { + size_t size = len - off > 0x8000 ? 0x8000 : len - off; - } //STM32F4END + printf("size: %zu\n", size); - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { - /* use fast word write. todo: half page. */ - uint32_t val; + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } -#if 0 /* todo: check write operation */ + off += size; + } + + /* Relock flash */ + lock_flash(sl); - uint32_t nwrites = sl->flash_pgsz; + } //STM32F4END - redo_write: + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + /* use fast word write. todo: half page. */ + uint32_t val; + uint32_t flash_regs_base; + uint32_t pagesize; + + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + pagesize = L0_WRITE_BLOCK_SIZE; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + pagesize = L1_WRITE_BLOCK_SIZE; + } -#endif /* todo: check write operation */ + /* todo: check write operation */ - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + /* disable pecr protection */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); - /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear\n"); - return -1; - } + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + if (val & (1 << 0)) { + fprintf(stderr, "pecr.pelock not clear\n"); + return -1; + } - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + /* unlock program memory */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } - off = 0; - if (len > L1_WRITE_BLOCK_SIZE) { - if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){ - /* This may happen on a blank device! */ + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + if (val & (1 << 1)) { + fprintf(stderr, "pecr.prglock not clear\n"); + return -1; + } + off = 0; + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { + /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); - } - else{ - off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; - } - } - - /* write remainingword in program memory */ - for ( ; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { - fprintf(stdout, "\r%3zd/%3zd pages written", - off/sl->flash_pgsz, len/sl->flash_pgsz); - fflush(stdout); - } - - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - - /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - } - -#if 0 /* todo: check redo write operation */ - - /* check written bytes. todo: should be on a per page basis. */ - data = stlink_read_debug32(sl, addr + off); - if (data == *(uint32_t*)(base + off)) { - /* re erase the page and redo the write operation */ - uint32_t page; - uint32_t val; - - /* fail if successive write count too low */ - if (nwrites < sl->flash_pgsz) { - fprintf(stderr, "writes operation failure count too high, aborting\n"); - return -1; - } - - nwrites = 0; - - /* assume addr aligned */ - if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); - page = addr + off; - - fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", - page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); - - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - - stlink_erase_flash_page(sl, page); - - goto redo_write; - } - - /* increment successive writes counter */ - ++nwrites; - -#endif /* todo: check redo write operation */ - } + } else { + off = (len / pagesize)*pagesize; + } + } + + /* write remainingword in program memory */ + for ( ; off < len; off += sizeof(uint32_t)) { + uint32_t data; + if (off > 254) + fprintf(stdout, "\r"); + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3zd/%3zd pages written", + off/sl->flash_pgsz, len/sl->flash_pgsz); + fflush(stdout); + } + + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); + + /* wait for sr.busy to be cleared */ + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) + ; + + /* todo: check redo write operation */ + + } fprintf(stdout, "\n"); - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID) { - ILOG("Starting Flash write for VL core id\n"); + /* reset lock bits */ + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || + sl->chip_id == STM32_CHIPID_F334 || + sl->chip_id == STM32_CHIPID_F37x) { + ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); + ELOG("init_flash_loader() == -1\n"); return -1; } @@ -1622,23 +1921,23 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned set_flash_cr_pg(sl); //DLOG("Finished setting flash cr pg, running loader!\n"); if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); return -1; } lock_flash(sl); if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); fflush(stdout); } } fprintf(stdout, "\n"); } else { - WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } - + return stlink_verify_write_flash(sl, addr, base, len); } @@ -1653,21 +1952,25 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { - WLOG("map_file() == -1\n"); + ELOG("map_file() == -1\n"); return -1; } for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; + if (mf.base[index] == erased_pattern) + num_empty ++; + else + num_empty = 0; } + /* Round down to words */ + num_empty -= (num_empty & 3); if(num_empty != 0) { - ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty); - mf.len -= num_empty; + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); /* set stack*/ @@ -1687,95 +1990,118 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! - WLOG("write_buffer_to_sram() == -1\n"); + ELOG("write_buffer_to_sram() == -1\n"); return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, target, 0); /* target */ - stlink_write_reg(sl, fl->buf_addr, 1); /* source */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - } else if (sl->core_id == STM32VL_CORE_ID) { - - size_t count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; + + /* setup core */ + stlink_write_reg(sl, target, 0); /* target */ + stlink_write_reg(sl, fl->buf_addr, 1); /* source */ + stlink_write_reg(sl, count, 2); /* count (32 bits words) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { + + size_t count = size / sizeof(uint16_t); + if (size % sizeof(uint16_t)) ++count; + + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ + stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { + + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; + if (sl->chip_id == STM32_CHIPID_L4) { + if (count % 2) ++count; + } - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count (32 bits words) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); - return -1; + fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); + return -1; } /* run loader */ stlink_run(sl); +#define WAIT_ROUNDS 10000 /* wait until done (reaches breakpoint) */ - while ((is_core_halted(sl) == 0) && (i <1000)) - { - i++; + for (i = 0; i < WAIT_ROUNDS; i++) { + usleep(10); + if (is_core_halted(sl)) + break; } - if ( i > 999) { - fprintf(stderr, "run error\n"); + if (i >= WAIT_ROUNDS) { + ELOG("flash loader run error\n"); return -1; } - + /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; - stlink_read_reg(sl, 3, &rr); - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } + stlink_read_reg(sl, 3, &rr); + if (rr.r[3] != count) { + fprintf(stderr, "write error, count == %u\n", rr.r[3]); + return -1; + } - } else if (sl->core_id == STM32VL_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } } else { - fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); - return -1; + fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); + return -1; }