X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=c122518bbc0864974cd09b50ab33ccafbda25c84;hb=cbd0cf0918d63753e8c35d779b4b04e1d87eb889;hp=937bf82963bf33ffb1cfa3d5e0de6230df899561;hpb=379fcb3c614d540e2d854700d77c80268b207b3f;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index 937bf82..c122518 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -59,8 +59,10 @@ #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 //STM32F4 @@ -134,7 +136,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32F4_CHIP_ID)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -146,7 +148,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -158,7 +160,7 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } @@ -179,12 +181,12 @@ static int unlock_flash_if(stlink_t *sl) { return -1; } } - ILOG("Successfully unlocked flash\n"); + DLOG("Successfully unlocked flash\n"); return 0; } static void lock_flash(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } @@ -197,7 +199,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -210,7 +212,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -227,26 +229,34 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_CR, n); + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) + stlink_write_debug32(sl, FLASH_F4_CR, + stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); + else + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_CR, n); + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) + stlink_write_debug32(sl, FLASH_F4_CR, + stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); + else + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); } static void set_flash_cr_strt(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); } else { - /* assume come on the flash_cr_per path */ - const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); - stlink_write_debug32(sl, FLASH_CR, n); + stlink_write_debug32( + sl, FLASH_CR, + stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) ); } } @@ -256,7 +266,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -265,7 +275,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } static inline unsigned int is_flash_busy(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -277,6 +287,22 @@ static void wait_flash_busy(stlink_t *sl) { ; } +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + while (is_flash_busy(sl)) + { + usleep(10000); + i++; + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + fprintf(stdout, "\n"); +} + static inline unsigned int is_flash_eop(stlink_t *sl) { return read_flash_sr(sl) & (1 << FLASH_SR_EOP); } @@ -394,22 +420,23 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; - sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); - /* Fix chip_id for F4 rev A errata */ - if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) { - chip_id = 0x413; + sl->chip_id = chip_id & 0xfff; + /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ + if (sl->chip_id == 0x411) { + uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); + if((cpuid & 0xfff0) == 0xc240) + sl->chip_id = 0x413; } - sl->chip_id = chip_id; - for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == (chip_id & 0xFFF)) { - params = &devices[i]; - break; - } - } + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); return -1; @@ -420,9 +447,9 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_base = STM32_SRAM_BASE; // read flash size from hardware, if possible... - if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + if (sl->chip_id == STM32_CHIPID_F2) { sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? - } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else { uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; @@ -537,6 +564,11 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); + if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour + fprintf(stderr, "Error: Data length > 64: +%d byte.\n", + len); + return; + } sl->backend->write_mem8(sl, addr, len); } @@ -716,15 +748,21 @@ static void unmap_file(mapped_file_t * mf) { mf->len = 0; } +/* Limit the block size to compare to 0x1800 + Anything larger will stall the STLINK2 + Maybe STLINK V1 needs smaller value!*/ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { size_t off; + size_t n_cmp = sl->flash_pgsz; + if ( n_cmp > 0x1800) + n_cmp = 0x1800; - for (off = 0; off < mf->len; off += sl->flash_pgsz) { + for (off = 0; off < mf->len; off += n_cmp) { size_t aligned_size; /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > mf->len) + size_t cmp_size = n_cmp; + if ((off + n_cmp) > mf->len) cmp_size = mf->len - off; aligned_size = cmp_size; @@ -792,6 +830,11 @@ int stlink_fwrite_sram /* success */ error = 0; + /* set stack*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + /* Set PC to the reset routine*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_run(sl); on_error: unmap_file(&mf); @@ -803,7 +846,8 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; - int num_zero = 0; + int num_empty = 0; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -811,6 +855,12 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) return -1; } + if (size <1) + size = sl->flash_size; + + if (size > sl->flash_size) + size = sl->flash_size; + /* do the copy by 1k blocks */ for (off = 0; off < size; off += 1024) { size_t read_size = 1024; @@ -827,10 +877,10 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + off, rounded_size); for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == 0) - num_zero ++; + if (sl->q_buf[index] == erased_pattern) + num_empty ++; else - num_zero = 0; + num_empty = 0; } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); @@ -839,7 +889,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } /* Ignore NULL Bytes at end of file */ - ftruncate(fd, size - num_zero); + ftruncate(fd, size - num_empty); /* success */ error = 0; @@ -852,8 +902,16 @@ on_error: int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { /* write the buffer right after the loader */ - memcpy(sl->q_buf, buf, size); - stlink_write_mem8(sl, fl->buf_addr, size); + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + stlink_write_mem32(sl, fl->buf_addr, chunk); + } + if (rem) { + memcpy(sl->q_buf, buf+chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem); + } return 0; } @@ -869,7 +927,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if(sl->chip_id == STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -886,8 +944,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - ILOG("Erasing flash page at addr: %#x\n", flashaddr); - if (sl->chip_id == STM32F4_CHIP_ID) + if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -915,7 +972,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } - else if (sl->core_id == STM32L_CORE_ID) + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { uint32_t val; @@ -1027,26 +1084,42 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy(sl); - - /* relock the flash */ - lock_flash(sl); - - /* todo: verify the erased memory */ - + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + /* erase each page */ + int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + /* addr must be an addr inside the page */ + stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + return -1; + } + fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fflush(stdout); + } + fprintf(stdout, "\n"); + } + else { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* set the mass erase bit */ + set_flash_cr_mer(sl); + + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); + + /* wait for completion */ + wait_flash_busy_progress(sl); + + /* relock the flash */ + lock_flash(sl); + + /* todo: verify the erased memory */ + } return 0; } @@ -1112,7 +1185,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->core_id == STM32L_CORE_ID) /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */ { loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); @@ -1164,7 +1237,7 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { */ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + if (sl->chip_id == STM32_CHIPID_F4) { DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); return 0; } @@ -1193,6 +1266,56 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) +{ + unsigned int count; + uint32_t val; + flash_loader_t fl; + + ILOG("Starting Half page flash write for STM32L core id\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } + /* Unlock already done */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} + +#define L1_WRITE_BLOCK_SIZE 0x80 + for (count = 0; count < num_half_pages; count ++) { + if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) { + WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + return -1; + } + /* wait for sr.busy to be cleared */ + if (sl->verbose >= 1) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages); + fflush(stdout); + } + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { + } + } + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~(1 << FLASH_L1_PROG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~(1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + + return 0; +} + int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; @@ -1227,17 +1350,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } + fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", + (unsigned long)addr + off); + fflush(stdout); page_count++; } + fprintf(stdout,"\n"); ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if (sl->chip_id == STM32F4_CHIP_ID) { + if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { /* todo: check write operation */ /* First unlock the cr */ unlock_flash_if(sl); + /* TODO: Check that Voltage range is 2.7 - 3.6 V */ /* set parallelisim to 32 bit*/ write_flash_cr_psiz(sl, 2); @@ -1276,7 +1404,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } //STM32F4END - else if (sl->core_id == STM32L_CORE_ID) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1309,19 +1437,28 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned fprintf(stderr, "pecr.prglock not clear\n"); return -1; } + off = 0; + if (len > L1_WRITE_BLOCK_SIZE) { + if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){ + /* This may happen on a blank device! */ + WLOG("\nwrite_half_pages failed == -1\n"); + } + else{ + off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; + } + } - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { + /* write remainingword in program memory */ + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (sl->verbose >= 1) { - if ((off & (sl->flash_pgsz - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = off / sl->flash_pgsz; - const uint32_t pgcount = len / sl->flash_pgsz; - fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount); - } - } + if (off > 254) + fprintf(stdout, "\r"); + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3u/%u pages written", + off/sl->flash_pgsz, len/sl->flash_pgsz); + fflush(stdout); + } write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); stlink_write_debug32(sl, addr + off, data); @@ -1369,6 +1506,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check redo write operation */ } + fprintf(stdout, "\n"); /* reset lock bits */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); @@ -1381,15 +1519,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } - /* write each page. above WRITE_BLOCK_SIZE fails? */ -#define WRITE_BLOCK_SIZE 0x40 int write_block_count = 0; - for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { - ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count, - WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE); + for (off = 0; off < len; off += sl->flash_pgsz) { /* adjust last write size */ - size_t size = WRITE_BLOCK_SIZE; - if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; + size_t size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > len) size = len - off; /* unlock and set programming mode */ unlock_flash_if(sl); @@ -1400,8 +1534,14 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } lock_flash(sl); - DLOG("Finished writing block %d\n", write_block_count++); + if (sl->verbose >= 1) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); + fflush(stdout); + } } + fprintf(stdout, "\n"); } else { WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; @@ -1420,23 +1560,29 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_zero = 0, index; + unsigned int num_empty = 0, index; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { WLOG("map_file() == -1\n"); return -1; } for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == 0) - num_zero ++; + if (mf.base[index] == erased_pattern) + num_empty ++; else - num_zero = 0; + num_empty = 0; } - if(num_zero != 0) { - ILOG("Ignoring %d bytes of Zeros at end of file\n",num_zero); - mf.len -= num_zero; + if(num_empty != 0) { + ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty); + mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); + /* set stack*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + /* Set PC to the reset routine*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_run(sl); unmap_file(&mf); return err; } @@ -1444,6 +1590,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; + int i = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { @@ -1452,7 +1599,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->core_id == STM32L_CORE_ID) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1461,7 +1608,6 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, target, 0); /* target */ stlink_write_reg(sl, fl->buf_addr, 1); /* source */ stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, 0, 3); /* output count */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->core_id == STM32VL_CORE_ID) { @@ -1485,10 +1631,18 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_run(sl); /* wait until done (reaches breakpoint) */ - while (is_core_halted(sl) == 0) ; + while ((is_core_halted(sl) == 0) && (i <1000)) + { + i++; + } + if ( i > 999) { + fprintf(stderr, "run error\n"); + return -1; + } + /* check written byte count */ - if (sl->core_id == STM32L_CORE_ID) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count;