X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=204491cf69f12e00dc0800fc6f8d922b59dcd748;hb=89c3b1462b8c4b96e2071a87883aed5e030bbef9;hp=6e327f02877a854ed2cac3aed54923e7cdac21ba;hpb=2daeabaead8c45bc8ead84c59391ece6c0bbcfac;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index 6e327f0..204491c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -63,8 +63,35 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + ((1lu<chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) - res = stlink_read_debug32(sl, FLASH_F4_CR); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) + stlink_read_debug32(sl, FLASH_F4_CR, &res); + else if (sl->chip_id == STM32_CHIPID_L4) + stlink_read_debug32(sl, STM32L4_FLASH_CR, &res); else - res = stlink_read_debug32(sl, FLASH_CR); + stlink_read_debug32(sl, FLASH_CR, &res); #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif @@ -164,11 +200,16 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ + uint32_t cr = read_flash_cr(sl); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ) - return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) + return cr & (1 << FLASH_F4_CR_LOCK); + else if (sl->chip_id == STM32_CHIPID_L4) + return cr & (1lu << STM32L4_FLASH_CR_LOCK); else - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + return cr & (1 << FLASH_CR_LOCK); } static void unlock_flash(stlink_t *sl) { @@ -178,9 +219,13 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + } else if (sl->chip_id == STM32_CHIPID_L4) { + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2); } else { stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); @@ -204,9 +249,13 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); + } else if (sl->chip_id == STM32_CHIPID_L4) { + const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK); + stlink_write_debug32(sl, STM32L4_FLASH_CR, n); } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); @@ -217,10 +266,16 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); + } else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } else { const uint32_t n = 1 << FLASH_CR_PG; stlink_write_debug32(sl, FLASH_CR, n); @@ -230,7 +285,8 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -247,56 +303,86 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + stlink_read_debug32(sl, FLASH_F4_CR, &val); + val |= 1 << FLASH_CR_MER; + stlink_write_debug32(sl, FLASH_F4_CR, val); + } else if (sl->chip_id == STM32_CHIPID_L4) { + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val &=~ STM32L4_FLASH_CR_OPBITS; + val |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + } else { + stlink_read_debug32(sl, FLASH_CR, &val); + val |= 1 << FLASH_CR_MER; + stlink_write_debug32(sl, FLASH_CR, val); + } } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); - else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + stlink_read_debug32(sl, FLASH_F4_CR, &val); + val &= ~(1 << FLASH_CR_MER); + stlink_write_debug32(sl, FLASH_F4_CR, val); + } else { + stlink_read_debug32(sl, FLASH_CR, &val); + val &= ~(1 << FLASH_CR_MER); + stlink_write_debug32(sl, FLASH_CR, val); + } } static void set_flash_cr_strt(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, x); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + val = read_flash_cr(sl); + val |= (1 << FLASH_F4_CR_STRT); + stlink_write_debug32(sl, FLASH_F4_CR, val); + } else if (sl->chip_id == STM32_CHIPID_L4) { + val = read_flash_cr(sl); + val |= (1lu << STM32L4_FLASH_CR_STRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); } else { - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + stlink_read_debug32(sl, FLASH_CR, &val); + val |= 1 << FLASH_CR_STRT; + stlink_write_debug32(sl, FLASH_CR, val); } } static inline uint32_t read_flash_acr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_ACR); + uint32_t acr; + stlink_read_debug32(sl, FLASH_ACR, &acr); + return acr; } static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) - res = stlink_read_debug32(sl, FLASH_F4_SR); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) + stlink_read_debug32(sl, FLASH_F4_SR, &res); + else if (sl->chip_id == STM32_CHIPID_L4) + stlink_read_debug32(sl, STM32L4_FLASH_SR, &res); else - res = stlink_read_debug32(sl, FLASH_SR); + stlink_read_debug32(sl, FLASH_SR, &res); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + else if (sl->chip_id == STM32_CHIPID_L4) + return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); } @@ -363,6 +449,21 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_F4_CR, x); } +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<backend->exit_dfu_mode(sl); } -uint32_t stlink_core_id(stlink_t *sl) { +void stlink_core_id(stlink_t *sl) { DLOG("*** stlink_core_id ***\n"); sl->backend->core_id(sl); if (sl->verbose > 2) stlink_print_data(sl); DLOG("core_id = 0x%08x\n", sl->core_id); - return sl->core_id; + return; } uint32_t stlink_chip_id(stlink_t *sl) { - uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); - if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address + uint32_t chip_id; + stlink_read_debug32(sl, 0xE0042000, &chip_id); + if (chip_id == 0) + stlink_read_debug32(sl, 0x40015800, &chip_id); //Try Corex M0 DBGMCU_IDCODE register address return chip_id; } @@ -414,7 +517,8 @@ uint32_t stlink_chip_id(stlink_t *sl) { * @param cpuid pointer to the result object */ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); + uint32_t raw; + stlink_read_debug32(sl, CM3_REG_CPUID, &raw); cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; @@ -430,14 +534,15 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; - sl->core_id = stlink_core_id(sl); + stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); uint32_t flash_size; sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { - uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); + uint32_t cpuid; + stlink_read_debug32(sl, 0xE000ED00, &cpuid); if ((cpuid & 0xfff0) == 0xc240) sl->chip_id = 0x413; } @@ -456,13 +561,15 @@ int stlink_load_device_params(stlink_t *sl) { // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3); + stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size); if (params->flash_size_reg & 2) flash_size = flash_size >>16; flash_size = flash_size & 0xffff; if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { @@ -572,10 +679,10 @@ int stlink_target_voltage(stlink_t *sl) { return voltage; } -uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { - uint32_t data = sl->backend->read_debug32(sl, addr); +void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + sl->backend->read_debug32(sl, addr, data); DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); - return data; + return; } void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -871,7 +978,9 @@ int stlink_fwrite_sram int error = -1; size_t off; + size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t val; if (map_file(&mf, path) == -1) { @@ -889,16 +998,23 @@ int stlink_fwrite_sram } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { fprintf(stderr, "addr too high\n"); goto on_error; - } else if ((addr & 3) || (mf.len & 3)) { + } else if (addr & 3) { /* todo */ - fprintf(stderr, "unaligned addr or size\n"); + fprintf(stderr, "unaligned addr\n"); goto on_error; } + + len = mf.len; + + if(len & 3) { + len -= len & 3; + } + /* do the copy by 1k blocks */ - for (off = 0; off < mf.len; off += 1024) { + for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > mf.len) - size = mf.len - off; + if ((off + size) > len) + size = len - off; memcpy(sl->q_buf, mf.base + off, size); @@ -909,6 +1025,11 @@ int stlink_fwrite_sram stlink_write_mem32(sl, addr + off, size); } + if(mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + len, mf.len - len); + } + /* check the file ha been written */ if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); @@ -918,9 +1039,11 @@ int stlink_fwrite_sram /* success */ error = 0; /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); on_error: @@ -933,9 +1056,6 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; - int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -949,38 +1069,26 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) if (size > sl->flash_size) size = sl->flash_size; - /* do the copy by 1k blocks */ - for (off = 0; off < size; off += 1024) { - size_t read_size = 1024; - size_t rounded_size; - size_t index; - if ((off + read_size) > size) - read_size = size - off; + size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; + for (off = 0; off < size; off += cmp_size) { + size_t aligned_size; - /* round size if needed */ - rounded_size = read_size; - if (rounded_size & 3) - rounded_size = (rounded_size + 4) & ~(3); + /* adjust last page size */ + if ((off + cmp_size) > size) + cmp_size = size - off; + + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + off, rounded_size); + stlink_read_mem32(sl, addr + off, aligned_size); - for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; - } - if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { - fprintf(stderr, "write() != read_size\n"); + if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) { + fprintf(stderr, "write() != aligned_size\n"); goto on_error; } } - /* Ignore NULL Bytes at end of file */ - if (!ftruncate(fd, size - num_empty)) { - error = -1; - } - /* success */ error = 0; @@ -1021,9 +1129,36 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } +uint32_t calculate_F7_sectornum(uint32_t flashaddr){ + flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + if(flashaddr<0x20000) return(flashaddr/0x8000); + else if(flashaddr<0x40000) return(4); + else return(flashaddr/0x40000) +4; + +} + +// Returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = sl->flash_size / 2; + if (flashaddr > banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return bker | flashaddr/sl->flash_pgsz; +} + uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1032,6 +1167,12 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } + else if (sl->chip_id == STM32_CHIPID_F7) { + uint32_t sector=calculate_F7_sectornum(flashaddr); + if (sector<4) sl->flash_pgsz=0x8000; + else if(sector<5) sl->flash_pgsz=0x20000; + else sl->flash_pgsz=0x40000; + } return (sl->flash_pgsz); } @@ -1044,7 +1185,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)|| (sl->chip_id == STM32_CHIPID_F4_DSI)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1052,15 +1194,29 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) unlock_flash_if(sl); /* select the page to erase */ - // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sl->chip_id == STM32_CHIPID_L4) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STM32_CHIPID_F7) { + // calculate the actual page from the address + uint32_t sector=calculate_F7_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_snb(sl, sector); + } else { + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); - //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... - if (sector >= 12) sector += 4; + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... + if (sector >= 12) sector += 4; - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector); + } /* start erase operation */ set_flash_cr_strt(sl); @@ -1074,9 +1230,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1087,14 +1243,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } /* check if the locks are set */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if((val & (1<<0))||(val & (1<<1))) { /* disable pecr protection */ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); return -1; @@ -1105,7 +1261,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); return -1; @@ -1123,8 +1279,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) * TEXANE: ok, if experience says so and it works for you, we comment * it. If someone has a problem, please drop an email. */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, STM32L_FLASH_SR, &val) + } while((val & (1 << 0)) != 0); #endif /* fix_to_be_confirmed */ @@ -1135,16 +1292,19 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) page erase command, even though PM0062 recommends to wait before it. Test shows that a few iterations is performed in the following loop before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); /* reset lock bits */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) - | (1 << 0) | (1 << 1) | (1 << 2); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F3_SMALL + || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { /* wait for ongoing op to finish */ @@ -1178,9 +1338,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1338,7 +1498,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x04, 0xe0, 0x0c, 0x68, - 0x04, 0x66, + 0x04, 0x60, 0x01, 0x33, 0x04, 0x31, 0x04, 0x30, @@ -1370,28 +1530,108 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x3c, 0x02, 0x40, }; + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0x92, 0x00, + + 0x08, 0x4b, + 0x62, 0xb1, + 0x04, 0x78, + 0x0c, 0x70, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x01, 0x00, + 0x01, 0xf1, 0x01, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + 0x00, 0xbf, + + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0x08, 0x4b, // start: ldr r3, [pc, #32] ; + 0x72, 0xb1, // next: cbz r2, + 0x04, 0x68, // ldr r4, [r0, #0] + 0x45, 0x68, // ldr r5, [r0, #4] + 0x0c, 0x60, // str r4, [r1, #0] + 0x4d, 0x60, // str r5, [r1, #4] + 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n + 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 + 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 + 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xef, 0xe7, // b.n + 0x00, 0xbe, // done: bkpt 0x0000 + 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + }; + + static const uint8_t loader_code_stm32f7[] = { + 0x08, 0x4b, + 0x72, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xef, 0xe7, + 0x00, 0xbe, // bkpt #0x00 + 0x00, 0x3c, 0x02, 0x40, + }; + const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F3_SMALL + || sl->chip_id == STM32_CHIPID_F303_HIGH + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } + } else if (sl->chip_id == STM32_CHIPID_F7){ + loader_code = loader_code_stm32f7; + loader_size = sizeof(loader_code_stm32f7); + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if (sl->chip_id == STM32_CHIPID_L0) { - loader_code = loader_code_stm32l0; - loader_size = sizeof(loader_code_stm32l0); - } else { + loader_code = loader_code_stm32l0; + loader_size = sizeof(loader_code_stm32l0); + } else if (sl->chip_id == STM32_CHIPID_L4) { + loader_code = loader_code_stm32l4; + loader_size = sizeof(loader_code_stm32l4); + } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1478,18 +1718,20 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin return -1; } /* Unlock already done */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {} + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); for (count = 0; count < num_half_pages; count ++) { if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return -1; @@ -1501,20 +1743,21 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) { - } + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); } - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", @@ -1560,15 +1803,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); + if (eraseonly) + return 0; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F7) || + (sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_F4_DSI)) { /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4\n"); + ILOG("Starting Flash write for F2/F4/L4\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); @@ -1579,8 +1829,30 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t unlock_flash_if(sl); /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - /* set parallelisim to 32 bit*/ - write_flash_cr_psiz(sl, 2); + if (sl->chip_id != STM32_CHIPID_L4) { + /* set parallelisim to 32 bit*/ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } + } else { + /* L4 does not have a byte-write mode */ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage < 1710) { + printf("Target voltage (%d mV) too low for flash writes!\n", voltage); + return -1; + } + } /* set programming mode */ set_flash_cr_pg(sl); @@ -1603,9 +1875,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1626,7 +1898,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); return -1; @@ -1637,7 +1909,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; @@ -1668,20 +1940,23 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); /* todo: check redo write operation */ } fprintf(stdout, "\n"); /* reset lock bits */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) - | (1 << 0) | (1 << 1) | (1 << 2); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F334 || sl->chip_id == STM32_CHIPID_F37x) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); @@ -1732,31 +2007,33 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; + unsigned int num_empty, index, val; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); return -1; } - for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; + index = mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--index] != erased_pattern) { + break; + } } /* Round down to words */ num_empty -= (num_empty & 3); if(num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - mf.len -= num_empty; } - err = stlink_write_flash(sl, addr, mf.base, mf.len); + err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len); /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); unmap_file(&mf); return err; @@ -1774,9 +2051,9 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1790,6 +2067,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -1804,10 +2083,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; + if (sl->chip_id == STM32_CHIPID_L4) { + if (count % 2) ++count; + } /* setup core */ stlink_write_reg(sl, fl->buf_addr, 0); /* source */ @@ -1837,9 +2120,9 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1853,6 +2136,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -1863,7 +2148,9 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_F4_DSI)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) {