X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=18c76fb86c109b242d32c7f8080a88d67941ca60;hb=d25244304547517f8b67e78a1fb52eaec165b18d;hp=9613080ba13f1c2eea60332c6d2dd3e45535ec4f;hpb=766138867ca4729497b989b89fc492fb2faa48f0;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index 9613080..18c76fb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -18,14 +18,6 @@ #define O_BINARY 0 #endif - -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define ELOG(format, args...) ugly_log(UERROR, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) - /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ @@ -71,6 +63,47 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + ((1lu< le (don't swap) @@ -130,24 +165,35 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_WRPR) & 0xff; + uint32_t rdp; + stlink_read_debug32(sl, FLASH_WRPR, &rdp); + return rdp & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_WRPR); + uint32_t wrpr; + stlink_read_debug32(sl, FLASH_WRPR, &wrpr); + return wrpr; } static inline uint32_t read_flash_obr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_OBR); + uint32_t obr; + stlink_read_debug32(sl, FLASH_OBR, &obr); + return obr; } static inline uint32_t read_flash_cr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - res = stlink_read_debug32(sl, FLASH_F4_CR); + uint32_t reg, res; + + if (sl->flash_type == FLASH_TYPE_F4) + reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + reg = STM32L4_FLASH_CR; else - res = stlink_read_debug32(sl, FLASH_CR); + reg = FLASH_CR; + + stlink_read_debug32(sl, reg, &res); + #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif @@ -156,28 +202,34 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); + uint32_t cr_lock_shift, cr = read_flash_cr(sl); + + if (sl->flash_type == FLASH_TYPE_F4) + cr_lock_shift = FLASH_F4_CR_LOCK; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_lock_shift = STM32L4_FLASH_CR_LOCK; else - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + cr_lock_shift = FLASH_CR_LOCK; + + return cr & (1 << cr_lock_shift); } static void unlock_flash(stlink_t *sl) { + uint32_t key_reg; /* the unlock sequence consists of 2 write cycles where 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. - */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); - } else { - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); - } + */ + if (sl->flash_type == FLASH_TYPE_F4) + key_reg = FLASH_F4_KEYR; + else if (sl->flash_type == FLASH_TYPE_L4) + key_reg = STM32L4_FLASH_KEYR; + else + key_reg = FLASH_KEYR; + stlink_write_debug32(sl, key_reg, FLASH_KEY1); + stlink_write_debug32(sl, key_reg, FLASH_KEY2); } static int unlock_flash_if(stlink_t *sl) { @@ -195,37 +247,56 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - stlink_write_debug32(sl, FLASH_F4_CR, n); + uint32_t cr_lock_shift, cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else { - /* write to 1 only. reset by hw at unlock sequence */ - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; } + + n = read_flash_cr(sl) | (1 << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_pg(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_CR_PG); - stlink_write_debug32(sl, FLASH_F4_CR, x); + uint32_t cr_reg, x; + + x = read_flash_cr(sl); + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= 1 << STM32L4_FLASH_CR_PG; } else { - const uint32_t n = 1 << FLASH_CR_PG; - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + x = 1 << FLASH_CR_PG; } + + stlink_write_debug32(sl, cr_reg, x); } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - stlink_write_debug32(sl, FLASH_F4_CR, n); + uint32_t cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) + cr_reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_reg = STM32L4_FLASH_CR; else - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + + n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_per(stlink_t *sl) { @@ -239,58 +310,94 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + } else { + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); - else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + } else { + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; + } + + stlink_read_debug32(sl, cr_reg, &val); + val &= ~cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr_strt(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, x); + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = 1 << STM32L4_FLASH_CR_STRT; } else { - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + cr_reg = FLASH_CR; + cr_strt = 1 << FLASH_CR_STRT; } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); } static inline uint32_t read_flash_acr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_ACR); + uint32_t acr; + stlink_read_debug32(sl, FLASH_ACR, &acr); + return acr; } static inline uint32_t read_flash_sr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - res = stlink_read_debug32(sl, FLASH_F4_SR); + uint32_t res, sr_reg; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_reg = FLASH_F4_SR; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_reg = STM32L4_FLASH_SR; else - res = stlink_read_debug32(sl, FLASH_SR); - //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); + sr_reg = FLASH_SR; + + stlink_read_debug32(sl, sr_reg, &res); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) - return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + uint32_t sr_busy_shift; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_busy_shift = FLASH_F4_SR_BSY; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_busy_shift = STM32L4_FLASH_SR_BSY; else - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + sr_busy_shift = FLASH_SR_BSY; + + return read_flash_sr(sl) & (1 << sr_busy_shift); } static void wait_flash_busy(stlink_t *sl) { @@ -355,59 +462,84 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_F4_CR, x); } -#if 0 /* todo */ - -static void disable_flash_read_protection(stlink_t *sl) { - /* erase the option byte area */ - /* rdp = 0x00a5; */ - /* reset */ +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<backend->close(sl); free(sl); } -void stlink_exit_debug_mode(stlink_t *sl) { +int stlink_exit_debug_mode(stlink_t *sl) { + int ret; + DLOG("*** stlink_exit_debug_mode ***\n"); - stlink_write_debug32(sl, DHCSR, DBGKEY); - sl->backend->exit_debug_mode(sl); + ret = stlink_write_debug32(sl, DHCSR, DBGKEY); + if (ret == -1) + return ret; + + return sl->backend->exit_debug_mode(sl); } -void stlink_enter_swd_mode(stlink_t *sl) { +int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); - sl->backend->enter_swd_mode(sl); + return sl->backend->enter_swd_mode(sl); } // Force the core into the debug mode -> halted state. -void stlink_force_debug(stlink_t *sl) { +int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - sl->backend->force_debug(sl); + return sl->backend->force_debug(sl); } -void stlink_exit_dfu_mode(stlink_t *sl) { +int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); - sl->backend->exit_dfu_mode(sl); + return sl->backend->exit_dfu_mode(sl); } -uint32_t stlink_core_id(stlink_t *sl) { +int stlink_core_id(stlink_t *sl) { + int ret; + DLOG("*** stlink_core_id ***\n"); - sl->backend->core_id(sl); + ret = sl->backend->core_id(sl); + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return ret; + } if (sl->verbose > 2) stlink_print_data(sl); DLOG("core_id = 0x%08x\n", sl->core_id); - return sl->core_id; + return ret; } -uint32_t stlink_chip_id(stlink_t *sl) { - uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); - if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address - return chip_id; +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + if (ret == -1) + return ret; + + if (*chip_id == 0) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address + + return ret; } /** @@ -415,13 +547,17 @@ uint32_t stlink_chip_id(stlink_t *sl) { * @param sl stlink context * @param cpuid pointer to the result object */ -void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { + uint32_t raw; + + if (stlink_read_debug32(sl, CM3_REG_CPUID, &raw)) + return -1; + cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; cpuid->revision = raw & 0xf; - return; + return 0; } /** @@ -432,13 +568,16 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; - sl->core_id = stlink_core_id(sl); - uint32_t chip_id = stlink_chip_id(sl); + stlink_core_id(sl); + uint32_t chip_id; + uint32_t flash_size; + stlink_chip_id(sl, &chip_id); sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { - uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); + uint32_t cpuid; + stlink_read_debug32(sl, 0xE000ED00, &cpuid); if ((cpuid & 0xfff0) == 0xc240) sl->chip_id = 0x413; } @@ -454,26 +593,25 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } + if (params->flash_type == FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + return -1; + } + + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - - // read flash size from hardware, if possible... - if (sl->chip_id == STM32_CHIPID_F2) { - sl->flash_size = 0x100000; /* Use maximum, User must care!*/ - } else if (sl->chip_id == STM32_CHIPID_F4 || - sl->chip_id == STM32_CHIPID_F4_LP) { - sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { - // if the flash size is zero, we assume it is 128k, if not we calculate the real value - uint32_t flash_size = stlink_read_debug32(sl,params->flash_size_reg) & 0xffff; - if ( flash_size == 0 ) { - sl->flash_size = 128 * 1024; - } else { - sl->flash_size = flash_size * 1024; - } + stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size); + if (params->flash_size_reg & 2) + flash_size = flash_size >>16; + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { - uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0x1; // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { sl->flash_size = 384 * 1024; @@ -481,41 +619,51 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = 256 * 1024; } } else { - uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; } + sl->flash_type = params->flash_type; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + //medium and low devices have the same chipid. ram size depends on flash size. + //STM32F100xx datasheet Doc ID 16455 Table 2 + if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + sl->sram_size = 0x1000; + } + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - sl->flash_pgsz); + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); return 0; } -void stlink_reset(stlink_t *sl) { +int stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); - sl->backend->reset(sl); + return sl->backend->reset(sl); } -void stlink_jtag_reset(stlink_t *sl, int value) { +int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); - sl->backend->jtag_reset(sl, value); + return sl->backend->jtag_reset(sl, value); } -void stlink_run(stlink_t *sl) { +int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); - sl->backend->run(sl); + return sl->backend->run(sl); } -void stlink_status(stlink_t *sl) { +int stlink_status(stlink_t *sl) { + int ret; + DLOG("*** stlink_status ***\n"); - sl->backend->status(sl); + ret = sl->backend->status(sl); stlink_core_stat(sl); + + return ret; } /** @@ -543,9 +691,11 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { return; } -void stlink_version(stlink_t *sl) { +int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); - sl->backend->version(sl); + if (sl->backend->version(sl)) + return -1; + _parse_version(sl, &sl->version); DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); @@ -559,6 +709,8 @@ void stlink_version(stlink_t *sl) { if (sl->version.swim_v == 0) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } + + return 0; } int stlink_target_voltage(stlink_t *sl) { @@ -566,85 +718,89 @@ int stlink_target_voltage(stlink_t *sl) { DLOG("*** reading target voltage\n"); if (sl->backend->target_voltage != NULL) { voltage = sl->backend->target_voltage(sl); - if (voltage != -1) { + if (voltage != -1) { DLOG("target voltage = %ldmV\n", voltage); - } else { + } else { DLOG("error reading target voltage\n"); - } + } } else { DLOG("reading voltage not supported by backend\n"); } return voltage; } -uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { - uint32_t data = sl->backend->read_debug32(sl, addr); - DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); - return data; +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + + return ret; } -void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); - sl->backend->write_debug32(sl, addr, data); + return sl->backend->write_debug32(sl, addr, data); } -void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - sl->backend->write_mem32(sl, addr, len); + return sl->backend->write_mem32(sl, addr, len); } -void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - sl->backend->read_mem32(sl, addr, len); + return sl->backend->read_mem32(sl, addr, len); } -void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); abort(); } - sl->backend->write_mem8(sl, addr, len); + return sl->backend->write_mem8(sl, addr, len); } -void stlink_read_all_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_regs(stlink_t *sl, reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); - sl->backend->read_all_regs(sl, regp); + return sl->backend->read_all_regs(sl, regp); } -void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); - sl->backend->read_all_unsupported_regs(sl, regp); + return sl->backend->read_all_unsupported_regs(sl, regp); } -void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { DLOG("*** stlink_write_reg\n"); - sl->backend->write_reg(sl, reg, idx); + return sl->backend->write_reg(sl, reg, idx); } -void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); - return; + return -1; } - sl->backend->read_reg(sl, r_idx, regp); + return sl->backend->read_reg(sl, r_idx, regp); } -void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { int r_convert; DLOG("*** stlink_read_unsupported_reg\n"); @@ -659,13 +815,13 @@ void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return; + return -1; } - sl->backend->read_unsupported_reg(sl, r_convert, regp); + return sl->backend->read_unsupported_reg(sl, r_convert, regp); } -void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { int r_convert; DLOG("*** stlink_write_unsupported_reg\n"); @@ -680,10 +836,10 @@ void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *re r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return; + return -1; } - sl->backend->write_unsupported_reg(sl, val, r_convert, regp); + return sl->backend->write_unsupported_reg(sl, val, r_convert, regp); } unsigned int is_core_halted(stlink_t *sl) { @@ -692,23 +848,23 @@ unsigned int is_core_halted(stlink_t *sl) { return sl->q_buf[0] == STLINK_CORE_HALTED; } -void stlink_step(stlink_t *sl) { +int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); - sl->backend->step(sl); + return sl->backend->step(sl); } int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return mode; - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return mode; - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return mode; + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return mode; + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return mode; + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return mode; } DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; @@ -759,17 +915,17 @@ void stlink_core_stat(stlink_t *sl) { return; switch (sl->q_buf[0]) { - case STLINK_CORE_RUNNING: - sl->core_stat = STLINK_CORE_RUNNING; - DLOG(" core status: running\n"); - return; - case STLINK_CORE_HALTED: - sl->core_stat = STLINK_CORE_HALTED; - DLOG(" core status: halted\n"); - return; - default: - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - fprintf(stderr, " core status: unknown\n"); + case STLINK_CORE_RUNNING: + sl->core_stat = STLINK_CORE_RUNNING; + DLOG(" core status: running\n"); + return; + case STLINK_CORE_HALTED: + sl->core_stat = STLINK_CORE_HALTED; + DLOG(" core status: halted\n"); + return; + default: + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + fprintf(stderr, " core status: unknown\n"); } } @@ -782,11 +938,11 @@ void stlink_print_data(stlink_t * sl) { for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { /* - if (sl->q_data_dir == Q_DATA_OUT) - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - else - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - */ + if (sl->q_data_dir == Q_DATA_OUT) + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + else + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + */ } fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]); } @@ -876,7 +1032,9 @@ int stlink_fwrite_sram int error = -1; size_t off; + size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t val; if (map_file(&mf, path) == -1) { @@ -894,16 +1052,23 @@ int stlink_fwrite_sram } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { fprintf(stderr, "addr too high\n"); goto on_error; - } else if ((addr & 3) || (mf.len & 3)) { + } else if (addr & 3) { /* todo */ - fprintf(stderr, "unaligned addr or size\n"); + fprintf(stderr, "unaligned addr\n"); goto on_error; } + + len = mf.len; + + if(len & 3) { + len -= len & 3; + } + /* do the copy by 1k blocks */ - for (off = 0; off < mf.len; off += 1024) { + for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > mf.len) - size = mf.len - off; + if ((off + size) > len) + size = len - off; memcpy(sl->q_buf, mf.base + off, size); @@ -914,6 +1079,11 @@ int stlink_fwrite_sram stlink_write_mem32(sl, addr + off, size); } + if(mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + len, mf.len - len); + } + /* check the file ha been written */ if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); @@ -923,9 +1093,11 @@ int stlink_fwrite_sram /* success */ error = 0; /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); on_error: @@ -938,9 +1110,6 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; - int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -949,43 +1118,31 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } if (size <1) - size = sl->flash_size; + size = sl->flash_size; if (size > sl->flash_size) - size = sl->flash_size; + size = sl->flash_size; - /* do the copy by 1k blocks */ - for (off = 0; off < size; off += 1024) { - size_t read_size = 1024; - size_t rounded_size; - size_t index; - if ((off + read_size) > size) - read_size = size - off; + size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; + for (off = 0; off < size; off += cmp_size) { + size_t aligned_size; - /* round size if needed */ - rounded_size = read_size; - if (rounded_size & 3) - rounded_size = (rounded_size + 4) & ~(3); - - stlink_read_mem32(sl, addr + off, rounded_size); - - for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; - } - if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { - fprintf(stderr, "write() != read_size\n"); + /* adjust last page size */ + if ((off + cmp_size) > size) + cmp_size = size - off; + + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); + + stlink_read_mem32(sl, addr + off, aligned_size); + + if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) { + fprintf(stderr, "write() != aligned_size\n"); goto on_error; } } - /* Ignore NULL Bytes at end of file */ - if (!ftruncate(fd, size - num_empty)) { - error = -1; - } - /* success */ error = 0; @@ -1011,25 +1168,66 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s } uint32_t calculate_F4_sectornum(uint32_t flashaddr){ + uint32_t offset = 0; flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x4000) return (0); - else if(flashaddr<0x8000) return(1); - else if(flashaddr<0xc000) return(2); - else if(flashaddr<0x10000) return(3); - else if(flashaddr<0x20000) return(4); - else return(flashaddr/0x20000)+4; + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + if (flashaddr<0x4000) return (offset + 0); + else if(flashaddr<0x8000) return(offset + 1); + else if(flashaddr<0xc000) return(offset + 2); + else if(flashaddr<0x10000) return(offset + 3); + else if(flashaddr<0x20000) return(offset + 4); + else return offset + (flashaddr/0x20000) +4; } +uint32_t calculate_F7_sectornum(uint32_t flashaddr){ + flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + if(flashaddr<0x20000) return(flashaddr/0x8000); + else if(flashaddr<0x40000) return(4); + else return(flashaddr/0x40000) +4; + +} + +// Returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = sl->flash_size / 2; + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return bker | flashaddr/sl->flash_pgsz; +} + uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector<4) sl->flash_pgsz=0x4000; - else if(sector<5) sl->flash_pgsz=0x10000; - else sl->flash_pgsz=0x20000; - } - return (sl->flash_pgsz); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sector>= 12) { + sector -= 12; + } + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; + } + else if (sl->chip_id == STM32_CHIPID_F7) { + uint32_t sector=calculate_F7_sectornum(flashaddr); + if (sector<4) sl->flash_pgsz=0x8000; + else if(sector<5) sl->flash_pgsz=0x20000; + else sl->flash_pgsz=0x40000; + } + return (sl->flash_pgsz); } /** @@ -1040,145 +1238,153 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); + if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); - /* unlock if locked */ - unlock_flash_if(sl); + /* unlock if locked */ + unlock_flash_if(sl); - /* select the page to erase */ - // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + /* select the page to erase */ + if (sl->chip_id == STM32_CHIPID_L4) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); - /* start erase operation */ - set_flash_cr_strt(sl); + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STM32_CHIPID_F7) { + // calculate the actual page from the address + uint32_t sector=calculate_F7_sectornum(flashaddr); - /* wait for completion */ - wait_flash_busy(sl); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); - /* relock the flash */ - //todo: fails to program if this is in - lock_flash(sl); -#if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); -#endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { - - uint32_t val; + write_flash_cr_snb(sl, sector); + } else { + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); - /* check if the locks are set */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if((val & (1<<0))||(val & (1<<1))) { - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); + + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... + if (sector >= 12) sector += 4; - /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; + write_flash_cr_snb(sl, sector); } - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + /* start erase operation */ + set_flash_cr_strt(sl); - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; + /* wait for completion */ + wait_flash_busy(sl); + + /* relock the flash */ + //todo: fails to program if this is in + lock_flash(sl); +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); +#endif + } else if (sl->flash_type == FLASH_TYPE_L0) { + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; } - } - /* unused: unlock the option byte block */ -#if 0 - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); + /* check if the locks are set */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if((val & (1<<0))||(val & (1<<1))) { + /* disable pecr protection */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); + + /* check pecr.pelock is cleared */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } - /* check pecr.optlock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 2)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } -#endif + /* unlock program memory */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); - /* set pecr.{erase,prog} */ - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + /* check pecr.prglock is cleared */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return -1; + } + } + /* set pecr.{erase,prog} */ + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); #if 0 /* fix_to_be_confirmed */ - /* wait for sr.busy to be cleared - MP: Test shows that busy bit is not set here. Perhaps, PM0062 is - wrong and we do not need to wait here for clearing the busy bit. - TEXANE: ok, if experience says so and it works for you, we comment - it. If someone has a problem, please drop an email. - */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; + /* wait for sr.busy to be cleared + * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + * wrong and we do not need to wait here for clearing the busy bit. + * TEXANE: ok, if experience says so and it works for you, we comment + * it. If someone has a problem, please drop an email. + */ + do { + stlink_read_debug32(sl, STM32L_FLASH_SR, &val) + } while((val & (1 << 0)) != 0); #endif /* fix_to_be_confirmed */ - /* write 0 to the first word of the page to be erased */ - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing - page erase command, even though PM0062 recommends to wait before it. - Test shows that a few iterations is performed in the following loop - before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; - - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->core_id == STM32F0_CORE_ID - || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F37x) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); + /* write 0 to the first word of the page to be erased */ + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + /* reset lock bits */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == FLASH_TYPE_F0) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); - /* unlock if locked */ - unlock_flash_if(sl); + /* unlock if locked */ + unlock_flash_if(sl); - /* set the page erase bit */ - set_flash_cr_per(sl); + /* set the page erase bit */ + set_flash_cr_per(sl); - /* select the page to erase */ - write_flash_ar(sl, flashaddr); + /* select the page to erase */ + write_flash_ar(sl, flashaddr); - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); - /* wait for completion */ - wait_flash_busy(sl); + /* wait for completion */ + wait_flash_busy(sl); - /* relock the flash */ - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return -1; - } + /* relock the flash */ + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return -1; + } - /* todo: verify the erased page */ + /* todo: verify the erased page */ - return 0; + return 0; } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { + if (sl->flash_type == FLASH_TYPE_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1188,7 +1394,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); return -1; } - fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages); fflush(stdout); } fprintf(stdout, "\n"); @@ -1275,13 +1481,13 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ 0x04, 0x26, // mov r6, #4 /* PGERR */ - // write_half_word: + // write_half_word: 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ 0x2B, 0x43, // orr r3, r5 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ - // busy: + // busy: 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ 0xFC, 0xD0, // beq busy @@ -1294,7 +1500,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ 0x00, 0x2A, // cmp r2, #0 0xF0, 0xD1, // bne write_half_word - // exit: + // exit: 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ 0xAB, 0x43, // bic r3, r5 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ @@ -1305,20 +1511,41 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count - r3, output, word count - */ + r2, output, remaining word count + */ - 0x00, 0x23, 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x50, 0xf8, 0x04, 0xcb, + 0x41, 0xf8, 0x04, 0xcb, + 0x01, 0x3a, - 0x93, 0x42, + 0x00, 0x2a, + 0xf8, 0xd3, + 0x00, 0xbe + }; + + static const uint8_t loader_code_stm32l0[] = { + + /* + r0, input, source addr + r1, input, dest addr + r2, input, word count + r2, output, remaining word count + */ + + 0x04, 0xe0, + + 0x04, 0x68, + 0x0c, 0x60, + 0x01, 0x3a, + 0x04, 0x31, + 0x04, 0x30, + + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1345,23 +1572,107 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x3c, 0x02, 0x40, }; + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0x92, 0x00, + + 0x08, 0x4b, + 0x62, 0xb1, + 0x04, 0x78, + 0x0c, 0x70, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x01, 0x00, + 0x01, 0xf1, 0x01, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + 0x00, 0xbf, + + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0x08, 0x4b, // start: ldr r3, [pc, #32] ; + 0x72, 0xb1, // next: cbz r2, + 0x04, 0x68, // ldr r4, [r0, #0] + 0x45, 0x68, // ldr r5, [r0, #4] + 0x0c, 0x60, // str r4, [r1, #0] + 0x4d, 0x60, // str r5, [r1, #4] + 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n + 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 + 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 + 0xef, 0xe7, // b.n + 0x00, 0xbe, // done: bkpt 0x0000 + 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + }; + + static const uint8_t loader_code_stm32f7[] = { + 0x08, 0x4b, + 0x72, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xef, 0xe7, + 0x00, 0xbe, // bkpt #0x00 + 0x00, 0x3c, 0x02, 0x40, + }; + const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F3_SMALL + || sl->chip_id == STM32_CHIPID_F303_HIGH + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } + } else if (sl->chip_id == STM32_CHIPID_F7){ + loader_code = loader_code_stm32f7; + loader_size = sizeof(loader_code_stm32f7); + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); + } else if (sl->chip_id == STM32_CHIPID_L0) { + loader_code = loader_code_stm32l0; + loader_size = sizeof(loader_code_stm32l0); + } else if (sl->chip_id == STM32_CHIPID_L4) { + loader_code = loader_code_stm32l4; + loader_size = sizeof(loader_code_stm32l4); } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; @@ -1428,12 +1739,20 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; + unsigned int num_half_pages = len / pagesize; uint32_t val; + uint32_t flash_regs_base; flash_loader_t fl; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + ILOG("Starting Half page flash write for STM32L core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1441,21 +1760,22 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns return -1; } /* Unlock already done */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); -#define L1_WRITE_BLOCK_SIZE 0x80 for (count = 0; count < num_half_pages; count ++) { - if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) { - WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return -1; } /* wait for sr.busy to be cleared */ @@ -1465,24 +1785,25 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - } + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); } - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", - len, len, addr, addr); + len, len, addr, addr); /* check addr range is inside the flash */ stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { @@ -1516,34 +1837,58 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t return -1; } fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", - (unsigned long)addr + off); + (unsigned long)addr + off); fflush(stdout); page_count++; } fprintf(stdout,"\n"); ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + page_count, sl->flash_pgsz, sl->flash_pgsz); + + if (eraseonly) + return 0; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { - /* todo: check write operation */ + if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) { + /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4\n"); + ILOG("Starting Flash write for F2/F4/L4\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); return -1; } - /* First unlock the cr */ - unlock_flash_if(sl); + /* First unlock the cr */ + unlock_flash_if(sl); - /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - /* set parallelisim to 32 bit*/ - write_flash_cr_psiz(sl, 2); + /* TODO: Check that Voltage range is 2.7 - 3.6 V */ + if (sl->chip_id != STM32_CHIPID_L4) { + /* set parallelisim to 32 bit*/ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } + } else { + /* L4 does not have a byte-write mode */ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage < 1710) { + printf("Target voltage (%d mV) too low for flash writes!\n", voltage); + return -1; + } + } - /* set programming mode */ - set_flash_cr_pg(sl); + /* set programming mode */ + set_flash_cr_pg(sl); for(off = 0; off < len;) { size_t size = len - off > 0x8000 ? 0x8000 : len - off; @@ -1558,85 +1903,60 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t off += size; } -#if 0 -#define PROGRESS_CHUNK_SIZE 0x1000 - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (sl->verbose >= 1) { - if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; - const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; - fprintf(stdout, "Writing %ukB chunk %u out of %u\n", - PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); - } - } - - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - - /* wait for sr.busy to be cleared */ - wait_flash_busy(sl); - - } -#endif - /* Relock flash */ - lock_flash(sl); - -#if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); -#endif + /* Relock flash */ + lock_flash(sl); } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { - /* use fast word write. todo: half page. */ - uint32_t val; - -#if 0 /* todo: check write operation */ + else if (sl->flash_type == FLASH_TYPE_L0) { + /* use fast word write. todo: half page. */ + uint32_t val; + uint32_t flash_regs_base; + uint32_t pagesize; - uint32_t nwrites = sl->flash_pgsz; - - redo_write: + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + pagesize = L0_WRITE_BLOCK_SIZE; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + pagesize = L1_WRITE_BLOCK_SIZE; + } -#endif /* todo: check write operation */ + /* todo: check write operation */ - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + /* disable pecr protection */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); - /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear\n"); - return -1; - } + /* check pecr.pelock is cleared */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + fprintf(stderr, "pecr.pelock not clear\n"); + return -1; + } - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + /* unlock program memory */ + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } - off = 0; - if (len > L1_WRITE_BLOCK_SIZE) { - if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1) { - /* This may happen on a blank device! */ + /* check pecr.prglock is cleared */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + fprintf(stderr, "pecr.prglock not clear\n"); + return -1; + } + off = 0; + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { + /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); - } else { - off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; - } - } + } else { + off = (len / pagesize)*pagesize; + } + } - /* write remainingword in program memory */ - for ( ; off < len; off += sizeof(uint32_t)) { + /* write remainingword in program memory */ + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; if (off > 254) fprintf(stdout, "\r"); @@ -1651,55 +1971,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; - -#if 0 /* todo: check redo write operation */ - - /* check written bytes. todo: should be on a per page basis. */ - data = stlink_read_debug32(sl, addr + off); - if (data == *(uint32_t*)(base + off)) { - /* re erase the page and redo the write operation */ - uint32_t page; - uint32_t val; - - /* fail if successive write count too low */ - if (nwrites < sl->flash_pgsz) { - fprintf(stderr, "writes operation failure count too high, aborting\n"); - return -1; - } - - nwrites = 0; - - /* assume addr aligned */ - if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); - page = addr + off; - - fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", - page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); - - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); - stlink_erase_flash_page(sl, page); + /* todo: check redo write operation */ - goto redo_write; - } - - /* increment successive writes counter */ - ++nwrites; - -#endif /* todo: check redo write operation */ - } + } fprintf(stdout, "\n"); - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { - ILOG("Starting Flash write for VL/F0 core id\n"); + /* reset lock bits */ + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == FLASH_TYPE_F0) { + ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); @@ -1724,7 +2009,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); fflush(stdout); } } @@ -1747,29 +2032,38 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH )?0:0xff; + unsigned int num_empty, index, val; + unsigned char erased_pattern; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); return -1; } - for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; + + if (sl->flash_type == FLASH_TYPE_L0) + erased_pattern = 0x00; + else + erased_pattern = 0xff; + + index = mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--index] != erased_pattern) { + break; + } } + /* Round down to words */ + num_empty -= (num_empty & 3); if(num_empty != 0) { - ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty); - mf.len -= num_empty; + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } - err = stlink_write_flash(sl, addr, mf.base, mf.len); + err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len); /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); unmap_file(&mf); return err; @@ -1779,6 +2073,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons reg rr; int i = 0; + size_t count = 0; + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { @@ -1787,47 +2083,27 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, target, 0); /* target */ - stlink_write_reg(sl, fl->buf_addr, 1); /* source */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { - - size_t count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - } else { - fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); - return -1; + if (sl->flash_type == FLASH_TYPE_F0) { + count = size / sizeof(uint16_t); + if (size % sizeof(uint16_t)) + ++count; + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { + count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) + ++count; + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; } + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count */ + stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* run loader */ stlink_run(sl); @@ -1845,40 +2121,10 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - stlink_read_reg(sl, 3, &rr); - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } - - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { - - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1; - } - - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { - - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } - - } else { - - fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); - return -1; - } return 0;