X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fstlink-common.c;h=18c76fb86c109b242d32c7f8080a88d67941ca60;hb=25deee1055cdea42a4b28597f36e612bec77a2a1;hp=dce100daaec73e7189d08d2cdabed792cc54b9f2;hpb=e43a737c3c9ffe56045181b306509c942fd9998a;p=fw%2Fstlink diff --git a/src/stlink-common.c b/src/stlink-common.c index dce100d..18c76fb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -251,7 +251,7 @@ static void lock_flash(stlink_t *sl) { if (sl->flash_type == FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_lock_shift = FLASH_F4_CR_LOCK; } else if (sl->flash_type == FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; @@ -481,6 +481,8 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { void stlink_close(stlink_t *sl) { DLOG("*** stlink_close ***\n"); + if (!sl) + return; sl->backend->close(sl); free(sl); } @@ -534,7 +536,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret == -1) return ret; - if (chip_id == 0) + if (*chip_id == 0) ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address return ret; @@ -591,6 +593,12 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } + if (params->flash_type == FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + return -1; + } + + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -702,7 +710,7 @@ int stlink_version(stlink_t *sl) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } - return -1; + return 0; } int stlink_target_voltage(stlink_t *sl) { @@ -726,7 +734,7 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); return ret; } @@ -1191,7 +1199,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { flashaddr -= STM32_FLASH_BASE; if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = sl->flash_size / 2; - if (flashaddr > banksize) { + if (flashaddr >= banksize) { flashaddr -= banksize; bker = 0x100; } @@ -1242,19 +1250,21 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STM32_CHIPID_F7) { // calculate the actual page from the address uint32_t sector=calculate_F7_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); } else { // calculate the actual page from the address uint32_t sector=calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... if (sector >= 12) sector += 4; @@ -1384,7 +1394,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); return -1; } - fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages); fflush(stdout); } fprintf(stdout, "\n"); @@ -1598,7 +1608,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0xfb, 0xd1, // bne.n 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 0xef, 0xe7, // b.n 0x00, 0xbe, // done: bkpt 0x0000 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 @@ -2063,7 +2073,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons reg rr; int i = 0; - size_t count; + size_t count = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 @@ -2077,19 +2087,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || - sl->flash_type == FLASH_TYPE_L4 || - sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - if (sl->chip_id == STM32_CHIPID_L4) { - if (count % 2) - ++count; - } - } else { - fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); - return -1; + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; } /* setup core */ @@ -2116,7 +2121,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - stlink_read_all_regs(sl, &rr); + stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1;