X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fsamd21%2Fsamd21.h;h=91ad52bf0f24718d25320f8d2d5b0407ce2f9a53;hb=7bcde16c96f05595969bceef76905aa2e285c66b;hp=73b3db8948040bbc824e6295307e559940bf9df1;hpb=c59892cd337162c63e5d7ba8e8eec779d201022d;p=fw%2Faltos diff --git a/src/samd21/samd21.h b/src/samd21/samd21.h index 73b3db89..91ad52bf 100644 --- a/src/samd21/samd21.h +++ b/src/samd21/samd21.h @@ -474,57 +474,61 @@ struct samd21_dmac_desc { #define SAMD21_DMAC_CHCTRLB_EVIE 3 #define SAMD21_DMAC_CHCTRLB_EVOE 4 #define SAMD21_DMAC_CHCTRLB_LVL 5 +#define SAMD21_DMAC_CHCTRLB_LVL_LVL0 0UL +#define SAMD21_DMAC_CHCTRLB_LVL_LVL1 1UL +#define SAMD21_DMAC_CHCTRLB_LVL_LVL2 2UL +#define SAMD21_DMAC_CHCTRLB_LVL_LVL3 3UL #define SAMD21_DMAC_CHCTRLB_TRIGSRC 8 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_DISABLE 0x00 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_RX(n) (0x01 + (n) * 2) -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_TX(n) (0x02 + (n) * 2) -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_OVF 0x0d -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC0 0x0e -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC1 0x0f -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC2 0x10 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC3 0x11 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_OVF 0x12 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC0 0x13 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC1 0x14 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_OVF 0x15 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC0 0x16 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC1 0x17 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_OVF 0x18 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC0 0x19 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC1 0x1a -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_OVF 0x1b -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC0 0x1c -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC1 0x1d -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_OVF 0x1e -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC0 0x1f -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC1 0x20 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_OVF 0x21 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC0 0x22 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC1 0x23 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_OVF 0x24 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC0 0x25 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC1 0x26 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_ADC_RESRDY 0x27 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_DAC_EMPTY 0x28 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_0 0x29 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_1 0x2a -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_0 0x2b -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_1 0x2c -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_OVF 0x2d -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC0 0x2e -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC1 0x2f -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC2 0x30 -#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC3 0x31 +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_DISABLE 0x00UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_RX(n) (0x01UL + (n) * 2UL) +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_TX(n) (0x02UL + (n) * 2UL) +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_OVF 0x0dUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC0 0x0eUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC1 0x0fUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC2 0x10UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC3 0x11UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_OVF 0x12UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC0 0x13UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC1 0x14UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_OVF 0x15UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC0 0x16UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC1 0x17UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_OVF 0x18UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC0 0x19UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC1 0x1aUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_OVF 0x1bUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC0 0x1cUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC1 0x1dUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_OVF 0x1eUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC0 0x1fUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC1 0x20UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_OVF 0x21UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC0 0x22UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC1 0x23UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_OVF 0x24UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC0 0x25UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC1 0x26UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_ADC_RESRDY 0x27UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_DAC_EMPTY 0x28UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_0 0x29UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_1 0x2aUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_0 0x2bUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_1 0x2cUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_OVF 0x2dUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC0 0x2eUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC1 0x2fUL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC2 0x30UL +#define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC3 0x31UL #define SAMD21_DMAC_CHCTRLB_TRIGACT 22 -#define SAMD21_DMAC_CHCTRLB_TRIGACT_BLOCK 0 -#define SAMD21_DMAC_CHCTRLB_TRIGACT_BEAT 2 -#define SAMD21_DMAC_CHCTRLB_TRIGACT_TRANSACTION 3 +#define SAMD21_DMAC_CHCTRLB_TRIGACT_BLOCK 0UL +#define SAMD21_DMAC_CHCTRLB_TRIGACT_BEAT 2UL +#define SAMD21_DMAC_CHCTRLB_TRIGACT_TRANSACTION 3UL #define SAMD21_DMAC_CHCTRLB_CMD 24 -#define SAMD21_DMAC_CHCTRLB_CMD_NOACT 0 -#define SAMD21_DMAC_CHCTRLB_CMD_SUSPEND 1 -#define SAMD21_DMAC_CHCTRLB_CMD_RESUME 2 +#define SAMD21_DMAC_CHCTRLB_CMD_NOACT 0UL +#define SAMD21_DMAC_CHCTRLB_CMD_SUSPEND 1UL +#define SAMD21_DMAC_CHCTRLB_CMD_RESUME 2UL #define SAMD21_DMAC_CHINTFLAG_TERR 0 #define SAMD21_DMAC_CHINTFLAG_TCMPL 1 @@ -536,15 +540,81 @@ struct samd21_dmac_desc { #define SAMD21_DMAC_DESC_BTCTRL_VALID 0 #define SAMD21_DMAC_DESC_BTCTRL_EVOSEL 1 +#define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_DISABLE 0UL +#define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_BLOCK 1UL +#define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_BEAT 3UL #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT 3 +#define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_NOACT 0UL +#define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_INT 1UL +#define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_SUSPEND 2UL +#define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_BOTH 3UL #define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE 8 -#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_BYTE 0 -#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_HWORD 1 -#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_WORD 2 +#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_BYTE 0UL +#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_HWORD 1UL +#define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_WORD 2UL #define SAMD21_DMAC_DESC_BTCTRL_SRCINC 10 #define SAMD21_DMAC_DESC_BTCTRL_DSTINC 11 #define SAMD21_DMAC_DESC_BTCTRL_STEPSEL 12 +#define SAMD21_DMAC_DESC_BTCTRL_STEPSEL_DST 0UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSEL_SRC 1UL #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE 13 +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X1 0UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X2 1UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X4 2UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X8 3UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X16 4UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X32 5UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X64 6UL +#define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X128 7UL + +struct samd21_eic { + vuint8_t ctrl; + vuint8_t status; + vuint8_t nmictrl; + vuint8_t nmiflag; + vuint32_t evctrl; + vuint32_t intenclr; + vuint32_t intenset; + + vuint32_t intflag; + vuint32_t wakeup; + vuint32_t config[2]; +}; + +extern struct samd21_eic samd21_eic; + +#define samd21_eic (*(struct samd21_eic *) 0x40001800) + +#define SAMD21_NUM_EIC 16 + +#define SAMD21_EIC_CTRL_ENABLE 1 +#define SAMD21_EIC_CTRL_SWRST 0 + +#define SAMD21_EIC_STATUS_SYNCBUSY 7 + +#define SAMD21_EIC_NMICTRL_NMIFILTEN 3 +#define SAMD21_EIC_NMICTRL_NMISENSE 0 + +#define SAMD21_EIC_NMIFLAG_NMI 0 + +#define SAMD21_EIC_EVCTRL_EXTINTEO(n) (n) + +#define SAMD21_EIC_INTENCLR_EXTINT(n) (n) + +#define SAMD21_EIC_INTENSET_EXTINT(n) (n) + +#define SAMD21_EIC_INTFLAG_EXTINT(n) (n) +#define SAMD21_EIC_WAKEUP_WAKEUPEN(n) (n) +#define SAMD21_EIC_CONFIG_N(n) ((n) >> 3) +#define SAMD21_EIC_CONFIG_SENSE(n) (((n) & 7) << 2) +#define SAMD21_EIC_CONFIG_FILTEN(n) (SAMD21_EIC_CONFIG_SENSE(n) + 3) +#define SAMD21_EIC_CONFIG_SENSE_NONE 0 +#define SAMD21_EIC_CONFIG_SENSE_RISE 1 +#define SAMD21_EIC_CONFIG_SENSE_FALL 2 +#define SAMD21_EIC_CONFIG_SENSE_BOTH 3 +#define SAMD21_EIC_CONFIG_SENSE_HIGH 4 +#define SAMD21_EIC_CONFIG_SENSE_LOW 5 +#define SAMD21_EIC_CONFIG_SENSE_MASK 7UL struct samd21_nvmctrl { vuint32_t ctrla; @@ -612,11 +682,17 @@ extern struct samd21_nvmctrl samd21_nvmctrl; #define SAMD21_NVMCTRL_PARAM_RWWEEP 20 #define SAMD21_NVMCTRL_PARAM_RWWEEP_MASK 0xfff +static inline uint32_t +samd21_nvmctrl_page_shift(void) +{ + return(3 + ((samd21_nvmctrl.param >> SAMD21_NVMCTRL_PARAM_PSZ) & + SAMD21_NVMCTRL_PARAM_PSZ_MASK)); +} + static inline uint32_t samd21_nvmctrl_page_size(void) { - return 1 << (3 + ((samd21_nvmctrl.param >> SAMD21_NVMCTRL_PARAM_PSZ) & - SAMD21_NVMCTRL_PARAM_PSZ_MASK)); + return 1 << samd21_nvmctrl_page_shift(); } uint32_t @@ -701,6 +777,14 @@ samd21_port_pmux_set(struct samd21_port *port, uint8_t pin, uint8_t func) (1 << SAMD21_PORT_PINCFG_PMUXEN)); } +static inline void +samd21_port_pmux_clr(struct samd21_port *port, uint8_t pin) +{ + samd21_port_pincfg_set(port, pin, + (0 << SAMD21_PORT_PINCFG_PMUXEN), + (1 << SAMD21_PORT_PINCFG_PMUXEN)); +} + struct samd21_adc { vuint8_t ctrla; vuint8_t refctrl; @@ -776,6 +860,7 @@ struct samd21_adc { #define SAMD21_ADC_SWTRIG_START 1 #define SAMD21_ADC_INPUTCTRL_MUXPOS 0 +# define SAMD21_ADC_INPUTCTRL_MUXPOS_TEMP 0x18 # define SAMD21_ADC_INPUTCTRL_MUXPOS_BANDGAP 0x19 # define SAMD21_ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC 0x1a # define SAMD21_ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC 0x1b @@ -1338,6 +1423,119 @@ samd21_usb_ep_curbk(uint8_t ep) return (samd21_usb.ep[ep].epstatus >> SAMD21_USB_EP_EPSTATUS_CURBK) & 1; } +/* evsys */ + +struct samd21_evsys { + vuint8_t ctrl; + vuint8_t reserved_01; + vuint16_t reserved_02; + vuint32_t channel; + vuint16_t user; + vuint16_t reserved_0a; + vuint32_t chstatus; + + vuint32_t intenclr; + vuint32_t intenset; + vuint32_t intflag; +}; + +extern struct samd21_evsys samd21_evsys; + +#define SAMD21_NUM_EVSYS 16 + +#define samd21_evsys (*(struct samd21_evsys *) 0x42000400) + +#define SAMD21_EVSYS_CONTROL_SWRST 0 +#define SAMD21_EVSYS_CONTROL_GCLKREQ 4 + +#define SAMD21_EVSYS_CHANNEL_CHANNEL 0 + +#define SAMD21_EVSYS_CHANNEL_SWEVT 8 + +#define SAMD21_EVSYS_CHANNEL_EVGEN 16 +#define SAMD21_EVSYS_CHANNEL_EVGEN_NONE 0x00 +#define SAMD21_EVSYS_CHANNEL_EVGEN_RTC_CMP(i) (0x01 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_OVF 0x03 +#define SAMD21_EVSYS_CHANNEL_EVGEN_PER(i) (0x04 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_EXTINT(i) (0x0c + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_DMAC_CH(i) (0x1e + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_OVF 0x22 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_TRG 0x23 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_CNT 0x29 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_MCX(i) (0x25 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_OVF 0x29 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_TRG 0x2a +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_CNT 0x2b +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_MCX(i) (0x2c + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_OVF 0x2e +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_TRG 0x2f +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_CNT 0x30 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_MCX(i) (0x31 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC3_OVF 0x33 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC3_MC(i) (0x34 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC4_OVF 0x36 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC4_MC(i) (0x37 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC5_OVF 0x39 +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC5_MC(i) (0x3a + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC6_OVF 0x3c +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC6_MC(i) (0x3d + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC7_OVF 0x3f +#define SAMD21_EVSYS_CHANNEL_EVGEN_TC7_MC(i) (0x40 + (i)) +#define SAMD21_EVSYS_CHANNEL_EVGEN_ADC_RESRDY 0x42 +#define SAMD21_EVSYS_CHANNEL_EVGEN_ADC_WINMON 0x43 +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP0 0x44 +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP1 0x45 +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_WIN0 0x46 +#define SAMD21_EVSYS_CHANNEL_EVGEN_DAC_EMPTY 0x47 +#define SAMD21_EVSYS_CHANNEL_EVGEN_PTC_EOC 0x48 +#define SAMD21_EVSYS_CHANNEL_EVGEN_PTC_WCOMP 0x49 +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP2 0x4a +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP3 0x4b +#define SAMD21_EVSYS_CHANNEL_EVGEN_AC_WIN1 0x4c +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_OVF 0x4d +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_TRG 0x4e +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_CNT 0x4f +#define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_MCX(i) (0x50 + (i)) + +#define SAMD21_EVSYS_CHANNEL_PATH 24 +#define SAMD21_EVSYS_CHANNEL_PATH_SYNCHRONOUS 0 +#define SAMD21_EVSYS_CHANNEL_PATH_RESYNCHRONIZED 1 +#define SAMD21_EVSYS_CHANNEL_PATH_ASYNCHRONOUS 2 + +#define SAMD21_EVSYS_CHANNEL_EDGESEL 26 +#define SAMD21_EVSYS_CHANNEL_EDGESEL_NO_EVT_OUTPUT 0 +#define SAMD21_EVSYS_CHANNEL_EDGESEL_RISING_EDGE 1 +#define SAMD21_EVSYS_CHANNEL_EDGESEL_FALLING_EDGE 2 +#define SAMD21_EVSYS_CHANNEL_EDGESEL_BOTH_EDGES 3 + +#define SAMD21_EVSYS_USER_USER 0 +#define SAMD21_EVSYS_USER_USER_DMAC_CH(n) (0x00 + (n)) +#define SAMD21_EVSYS_USER_USER_TCC0_EV(n) (0x04 + (n)) +#define SAMD21_EVSYS_USER_USER_TCC0_MC(n) (0x06 + (n)) +#define SAMD21_EVSYS_USER_USER_TCC1_EV(n) (0x0a + (n)) +#define SAMD21_EVSYS_USER_USER_TCC1_MC(n) (0x0c + (n)) +#define SAMD21_EVSYS_USER_USER_TCC2_EV(n) (0x0e + (n)) +#define SAMD21_EVSYS_USER_USER_TCC2_MC(n) (0x10 + (n)) +#define SAMD21_EVSYS_USER_USER_TC(n) (0x12 + (n)) +#define SAMD21_EVSYS_USER_USER_ADC_START (0x17) +#define SAMD21_EVSYS_USER_USER_ADC_SYNC 0x18 +#define SAMD21_EVSYS_USER_USER_AC_COMP0 0x19 +#define SAMD21_EVSYS_USER_USER_AC_COMP1 0x1a +#define SAMD21_EVSYS_USER_USER_DAC_START 0x1b +#define SAMD21_EVSYS_USER_USER_PTC_STCONV 0x1c +#define SAMD21_EVSYS_USER_USER_AC_COMP2 0x1d +#define SAMD21_EVSYS_USER_USER_AC_COMP3 0x1e +#define SAMD21_EVSYS_USER_USER_TCC3_EV(n) (0x1f + (n)) +#define SAMD21_EVSYS_USER_USER_TCC3_MC(n) (0x21 + (n)) + +#define SAMD21_EVSYS_USER_CHANNEL 8 +#define SAMD21_EVSYS_USER_CHANNEL_NONE 0 +#define SAMD21_EVSYS_USER_CHANNEL_NUM(n) ((n) + 1) + + +#define SAMD21_EVSYS_CHSTATUS_USRRDY(n) (((n) & 7) | (((n) & 8) << 1)) +#define SAMD21_EVSYS_CHSTATUS_CHBUSY(n) (((n) & 7) | (((n) & 8) << 1) | 8) + /* sercom */ struct samd21_sercom { @@ -1378,6 +1576,8 @@ extern struct samd21_sercom samd21_sercom3; extern struct samd21_sercom samd21_sercom4; extern struct samd21_sercom samd21_sercom5; +#define SAMD21_NUM_SERCOM 6 + #define samd21_sercom0 (*(struct samd21_sercom *) 0x42000800) #define samd21_sercom1 (*(struct samd21_sercom *) 0x42000c00) #define samd21_sercom2 (*(struct samd21_sercom *) 0x42001000) @@ -1389,7 +1589,10 @@ extern struct samd21_sercom samd21_sercom5; #define SAMD21_SERCOM_CTRLA_ENABLE 1 #define SAMD21_SERCOM_CTRLA_MODE 2 # define SAMD21_SERCOM_CTRLA_MODE_USART 1 -# define SAMD21_SERCOM_CTRLA_MODE_I2C_LEADER 5 +# define SAMD21_SERCOM_CTRLA_MODE_SPI_CLIENT 2 +# define SAMD21_SERCOM_CTRLA_MODE_SPI_HOST 3 +# define SAMD21_SERCOM_CTRLA_MODE_I2C_CLIENT 4 +# define SAMD21_SERCOM_CTRLA_MODE_I2C_HOST 5 #define SAMD21_SERCOM_CTRLA_RUNSTDBY 7 @@ -1425,6 +1628,28 @@ extern struct samd21_sercom samd21_sercom5; #define SAMD21_SERCOM_CTRLA_INACTOUT_205US 3 #define SAMD21_SERCOM_CTRLA_LOWTOUT 30 +/* SPI controller mode */ +#define SAMD21_SERCOM_CTRLA_DOPO 16 +#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_1 0UL +#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_2_SCLK_3 1UL +#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_3_SCLK_1 2UL +#define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_3 3UL +#define SAMD21_SERCOM_CTRLA_DOPO_MASK 3UL + +#define SAMD21_SERCOM_CTRLA_DIPO 20 +#define SAMD21_SERCOM_CTRLA_DIPO_MISO_0 0UL +#define SAMD21_SERCOM_CTRLA_DIPO_MISO_1 1UL +#define SAMD21_SERCOM_CTRLA_DIPO_MISO_2 2UL +#define SAMD21_SERCOM_CTRLA_DIPO_MISO_3 3UL +#define SAMD21_SERCOM_CTRLA_DIPO_MASK 3UL + +#define SAMD21_SERCOM_CTRLA_FORM 24 +#define SAMD21_SERCOM_CTRLA_CPHA 28 +#define SAMD21_SERCOM_CTRLA_CPOL 29 +#define SAMD21_SERCOM_CTRLA_DORD 30 +#define SAMD21_SERCOM_CTRLA_DORD_LSB 1 +#define SAMD21_SERCOM_CTRLA_DORD_MSB 0 + /* USART mode */ #define SAMD21_SERCOM_CTRLB_CHSIZE 0 #define SAMD21_SERCOM_CTRLB_SBMODE 6 @@ -1449,6 +1674,15 @@ extern struct samd21_sercom samd21_sercom5; #define SAMD21_SERCOM_CTRLB_ACKACT_NACK 1 #define SAMD21_SERCOM_CTRLB_FIFOCLR 22 +/* SPI mode */ +#define SAMD21_SERCOM_CTRLB_CHSIZE 0 +# define SAMD21_SERCOM_CTRLB_CHSIZE_8 0 +#define SAMD21_SERCOM_CTRLB_PLOADEN 6 +#define SAMD21_SERCOM_CTRLB_SSDE 9 +#define SAMD21_SERCOM_CTRLB_MSSEN 13 +#define SAMD21_SERCOM_CTRLB_AMODE 14 +#define SAMD21_SERCOM_CTRLB_RXEN 17 + /* USART mode */ #define SAMD21_SERCOM_INTFLAG_DRE 0 #define SAMD21_SERCOM_INTFLAG_TXC 1 @@ -1465,6 +1699,9 @@ extern struct samd21_sercom samd21_sercom5; #define SAMD21_SERCOM_INTFLAG_SB 1 #define SAMD21_SERCOM_INTFLAG_MB 0 +/* SPI mode */ +#define SAMD21_SERCOM_INTFLAG_SSL 3 + #define SAMD21_SERCOM_INTENCLR_DRE 0 #define SAMD21_SERCOM_INTENCLR_TXC 1 #define SAMD21_SERCOM_INTENCLR_RXC 2 @@ -1476,10 +1713,10 @@ extern struct samd21_sercom samd21_sercom5; #define SAMD21_SERCOM_STATUS_PERR 0 #define SAMD21_SERCOM_STATUS_FERR 1 #define SAMD21_SERCOM_STATUS_BUFOVF 2 -#define SAMD21_SERCOM_STATUS_CTS 3 -#define SAMD21_SERCOM_STATUS_ISF 4 +#define SAMD21_SERCOM_STATUS_CTS 3 +#define SAMD21_SERCOM_STATUS_ISF 4 #define SAMD21_SERCOM_STATUS_COLL 5 -#define SAMD21_SERCOM_STATUS_TXE 6 +#define SAMD21_SERCOM_STATUS_TXE 6 #define SAMD21_SERCOM_SYNCBUSY_SWRST 0 #define SAMD21_SERCOM_SYNCBUSY_ENABLE 1