X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32l4x.h;h=7b9162b08606f8658476f022058bd65515b31abd;hb=6c1e1a212a8c044ae778c526851fe909bf219e90;hp=3e810a03ce7ef034b6e4fa6e41093d6edc7e0fcc;hpb=dc43ecce5a7ee5722ea851707ad3acd08a42b5aa;p=fw%2Fopenocd

diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 3e810a03c..7b9162b08 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -19,32 +19,44 @@
 #ifndef OPENOCD_FLASH_NOR_STM32L4X
 #define OPENOCD_FLASH_NOR_STM32L4X
 
+/* IMPORTANT: this file is included by stm32l4x driver and flashloader,
+ * so please when changing this file, do not forget to check the flashloader */
+
+/* FIXME: #include "helper/bits.h" cause build errors when compiling
+ * the flashloader, for now just redefine the needed 'BIT 'macro */
+
+#ifndef BIT
+#define BIT(nr)                 (1UL << (nr))
+#endif
+
 /* FLASH_CR register bits */
-#define FLASH_PG				(1 << 0)
-#define FLASH_PER				(1 << 1)
-#define FLASH_MER1				(1 << 2)
+#define FLASH_PG				BIT(0)
+#define FLASH_PER				BIT(1)
+#define FLASH_MER1				BIT(2)
 #define FLASH_PAGE_SHIFT		3
-#define FLASH_CR_BKER			(1 << 11)
-#define FLASH_MER2				(1 << 15)
-#define FLASH_STRT				(1 << 16)
-#define FLASH_OPTSTRT			(1 << 17)
-#define FLASH_EOPIE				(1 << 24)
-#define FLASH_ERRIE				(1 << 25)
-#define FLASH_OBL_LAUNCH		(1 << 27)
-#define FLASH_OPTLOCK			(1 << 30)
-#define FLASH_LOCK				(1 << 31)
+#define FLASH_BKER				BIT(11)
+#define FLASH_BKER_G0			BIT(13)
+#define FLASH_MER2				BIT(15)
+#define FLASH_STRT				BIT(16)
+#define FLASH_OPTSTRT			BIT(17)
+#define FLASH_EOPIE				BIT(24)
+#define FLASH_ERRIE				BIT(25)
+#define FLASH_OBL_LAUNCH		BIT(27)
+#define FLASH_OPTLOCK			BIT(30)
+#define FLASH_LOCK				BIT(31)
 
 /* FLASH_SR register bits */
-#define FLASH_BSY				(1 << 16)
+#define FLASH_BSY				BIT(16)
+#define FLASH_BSY2				BIT(17)
 
 /* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR			(1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR			(1 << 6) /* Size error */
-#define FLASH_PGAERR			(1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR			(1 << 4) /* Write protection error */
-#define FLASH_PROGERR			(1 << 3) /* Programming error */
-#define FLASH_OPERR				(1 << 1) /* Operation error */
-#define FLASH_EOP				(1 << 0) /* End of operation */
+#define FLASH_PGSERR			BIT(7) /* Programming sequence error */
+#define FLASH_SIZERR			BIT(6) /* Size error */
+#define FLASH_PGAERR			BIT(5) /* Programming alignment error */
+#define FLASH_WRPERR			BIT(4) /* Write protection error */
+#define FLASH_PROGERR			BIT(3) /* Programming error */
+#define FLASH_OPERR				BIT(1) /* Operation error */
+#define FLASH_EOP				BIT(0) /* End of operation */
 #define FLASH_ERROR				(FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
 								FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
 
@@ -56,15 +68,28 @@
 #define OPTKEY1					0x08192A3B
 #define OPTKEY2					0x4C5D6E7F
 
-#define RDP_LEVEL_0				0xAA
-#define RDP_LEVEL_1				0xBB
-#define RDP_LEVEL_2				0xCC
+/* FLASH_OPTR register bits */
+#define FLASH_RDP_MASK			0xFF
+#define FLASH_TZEN				BIT(31)
+
+/* FLASH secure block based bank 1/2 register offsets */
+#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
+#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
+
+#define FLASH_SECBB_SECURE      0xFFFFFFFF
+#define FLASH_SECBB_NON_SECURE  0
 
 /* other registers */
 #define DBGMCU_IDCODE_G0		0x40015800
 #define DBGMCU_IDCODE_L4_G4		0xE0042000
 #define DBGMCU_IDCODE_L5		0xE0044000
+#define UID64_DEVNUM			0x1FFF7580
+#define UID64_IDS				0x1FFF7584
+#define UID64_IDS_STM32WL		0x0080E115
 
 #define STM32_FLASH_BANK_BASE	0x08000000
+#define STM32_FLASH_S_BANK_BASE	0x0C000000
+
+#define STM32L5_REGS_SEC_OFFSET 0x10000000
 
 #endif