X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f2x.c;h=58edca7e1be9a5f6723b345c1cb6a9805d58ed77;hb=13cd75b6ecfd8d9cf04e56b182b6a162ad50247c;hp=0e4abb533c6ff672f50a20d752e64be57c957120;hpb=7719e9618e753ac41a46a2488dfba549ac578891;p=fw%2Fopenocd diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c index 0e4abb533..58edca7e1 100644 --- a/src/flash/nor/stm32f2x.c +++ b/src/flash/nor/stm32f2x.c @@ -29,7 +29,7 @@ #include "imp.h" #include #include -#include +#include /* Regarding performance: * @@ -55,7 +55,7 @@ * can be very different. * * To reduce testing complexity and dangers of regressions, - * a seperate file is used for stm32fx2x. + * a separate file is used for stm32fx2x. * * Sector sizes in kiBytes: * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128. @@ -123,6 +123,19 @@ /* Mass erase time can be as high as 32 s in x8 mode. */ #define FLASH_MASS_ERASE_TIMEOUT 33000 +#define FLASH_BANK_BASE 0x80000000 + +#define STM32F2_OTP_SIZE 512 +#define STM32F2_OTP_SECTOR_SIZE 32 +#define STM32F2_OTP_BANK_BASE 0x1fff7800 +#define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE)) + +/* see RM0410 section 3.6 "One-time programmable bytes" */ +#define STM32F7_OTP_SECTOR_SIZE 64 +#define STM32F7_OTP_SIZE 1024 +#define STM32F7_OTP_BANK_BASE 0x1ff0f000 +#define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE)) + #define STM32_FLASH_BASE 0x40023c00 #define STM32_FLASH_ACR 0x40023c00 #define STM32_FLASH_KEYR 0x40023c04 @@ -143,9 +156,8 @@ #define FLASH_PSIZE_16 (1 << 8) #define FLASH_PSIZE_32 (2 << 8) #define FLASH_PSIZE_64 (3 << 8) -/* The sector number encoding is not straight binary for dual bank flash. - * Warning: evaluates the argument multiple times */ -#define FLASH_SNB(a) ((((a) >= 12) ? 0x10 | ((a) - 12) : (a)) << 3) +/* The sector number encoding is not straight binary for dual bank flash. */ +#define FLASH_SNB(a) ((a) << 3) #define FLASH_LOCK (1 << 31) /* FLASH_SR register bits */ @@ -186,15 +198,59 @@ struct stm32x_options { struct stm32x_flash_bank { struct stm32x_options option_bytes; - int probed; + bool probed; + bool otp_unlocked; bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */ bool has_extra_options; /* F42x/43x/469/479/7xx */ bool has_boot_addr; /* F7xx */ bool has_optcr2_pcrop; /* F72x/73x */ - int protection_bits; /* F413/423 */ + unsigned int protection_bits; /* F413/423 */ uint32_t user_bank_size; }; +static bool stm32x_is_otp(struct flash_bank *bank) +{ + return bank->base == STM32F2_OTP_BANK_BASE || + bank->base == STM32F7_OTP_BANK_BASE; +} + +static bool stm32x_otp_is_f7(struct flash_bank *bank) +{ + return bank->base == STM32F7_OTP_BANK_BASE; +} + +static int stm32x_is_otp_unlocked(struct flash_bank *bank) +{ + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; + + return stm32x_info->otp_unlocked; +} + +static int stm32x_otp_disable(struct flash_bank *bank) +{ + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; + + LOG_INFO("OTP memory bank #%u is disabled for write commands.", + bank->bank_number); + stm32x_info->otp_unlocked = false; + return ERROR_OK; +} + +static int stm32x_otp_enable(struct flash_bank *bank) +{ + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; + + if (!stm32x_info->otp_unlocked) { + LOG_INFO("OTP memory bank #%u is is enabled for write commands.", + bank->bank_number); + stm32x_info->otp_unlocked = true; + } else { + LOG_WARNING("OTP memory bank #%u is is already enabled for write commands.", + bank->bank_number); + } + return ERROR_OK; +} + /* flash bank stm32x 0 0 */ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command) @@ -207,7 +263,8 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command) stm32x_info = malloc(sizeof(struct stm32x_flash_bank)); bank->driver_priv = stm32x_info; - stm32x_info->probed = 0; + stm32x_info->probed = false; + stm32x_info->otp_unlocked = false; stm32x_info->user_bank_size = bank->size; return ERROR_OK; @@ -235,7 +292,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout) retval = stm32x_get_flash_status(bank, &status); if (retval != ERROR_OK) return retval; - LOG_DEBUG("status: 0x%" PRIx32 "", status); + LOG_DEBUG("status: 0x%" PRIx32, status); if ((status & FLASH_BSY) == 0) break; if (timeout-- <= 0) { @@ -253,6 +310,8 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout) /* Clear but report errors */ if (status & FLASH_ERROR) { + if (retval == ERROR_OK) + retval = ERROR_FAIL; /* If this operation fails, we ignore it and report the original * retval */ @@ -290,7 +349,7 @@ static int stm32x_unlock_reg(struct target *target) return retval; if (ctrl & FLASH_LOCK) { - LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl); + LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32, ctrl); return ERROR_TARGET_FAILURE; } @@ -322,7 +381,7 @@ static int stm32x_unlock_option_reg(struct target *target) return retval; if (ctrl & OPTCR_LOCK) { - LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl); + LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl); return ERROR_TARGET_FAILURE; } @@ -360,7 +419,7 @@ static int stm32x_read_options(struct flash_bank *bank) if (retval != ERROR_OK) return retval; - /* FLASH_OPTCR1 has quite diffent meanings ... */ + /* FLASH_OPTCR1 has quite different meanings ... */ if (stm32x_info->has_boot_addr) { /* for F7xx it contains boot0 and boot1 */ stm32x_info->option_bytes.boot_addr = optiondata; @@ -459,14 +518,68 @@ static int stm32x_write_options(struct flash_bank *bank) return ERROR_OK; } +static int stm32x_otp_read_protect(struct flash_bank *bank) +{ + struct target *target = bank->target; + uint32_t lock_base; + int retval; + uint8_t lock; + + lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE + : STM32F2_OTP_LOCK_BASE; + + for (unsigned int i = 0; i < bank->num_sectors; i++) { + retval = target_read_u8(target, lock_base + i, &lock); + if (retval != ERROR_OK) + return retval; + bank->sectors[i].is_protected = !lock; + } + + return ERROR_OK; +} + +static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first, + unsigned int last) +{ + struct target *target = bank->target; + uint32_t lock_base; + int i, retval; + uint8_t lock; + + assert((first <= last) && (last < bank->num_sectors)); + + lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE + : STM32F2_OTP_LOCK_BASE; + + for (i = first; first <= last; i++) { + retval = target_read_u8(target, lock_base + i, &lock); + if (retval != ERROR_OK) + return retval; + if (lock) + continue; + + lock = 0xff; + retval = target_write_u8(target, lock_base + i, lock); + if (retval != ERROR_OK) + return retval; + } + + return ERROR_OK; +} + static int stm32x_protect_check(struct flash_bank *bank) { struct stm32x_flash_bank *stm32x_info = bank->driver_priv; struct flash_sector *prot_blocks; - int num_prot_blocks; + unsigned int num_prot_blocks; + int retval; + + /* if it's the OTP bank, look at the lock bits there */ + if (stm32x_is_otp(bank)) + return stm32x_otp_read_protect(bank); /* read write protection settings */ - int retval = stm32x_read_options(bank); + retval = stm32x_read_options(bank); if (retval != ERROR_OK) { LOG_DEBUG("unable to read option bytes"); return retval; @@ -480,19 +593,25 @@ static int stm32x_protect_check(struct flash_bank *bank) prot_blocks = bank->sectors; } - for (int i = 0; i < num_prot_blocks; i++) + for (unsigned int i = 0; i < num_prot_blocks; i++) prot_blocks[i].is_protected = ~(stm32x_info->option_bytes.protection >> i) & 1; return ERROR_OK; } -static int stm32x_erase(struct flash_bank *bank, int first, int last) +static int stm32x_erase(struct flash_bank *bank, unsigned int first, + unsigned int last) { + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; struct target *target = bank->target; - int i; - assert((0 <= first) && (first <= last) && (last < bank->num_sectors)); + if (stm32x_is_otp(bank)) { + LOG_ERROR("Cannot erase OTP memory"); + return ERROR_FAIL; + } + + assert((first <= last) && (last < bank->num_sectors)); if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); @@ -515,17 +634,21 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last) 4. Wait for the BSY bit to be cleared */ - for (i = first; i <= last; i++) { + for (unsigned int i = first; i <= last; i++) { + unsigned int snb; + if (stm32x_info->has_large_mem && i >= (bank->num_sectors / 2)) + snb = (i - (bank->num_sectors / 2)) | 0x10; + else + snb = i; + retval = target_write_u32(target, - stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT); + stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT); if (retval != ERROR_OK) return retval; retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT); if (retval != ERROR_OK) return retval; - - bank->sectors[i].is_erased = 1; } retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK); @@ -535,7 +658,8 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last) return ERROR_OK; } -static int stm32x_protect(struct flash_bank *bank, int set, int first, int last) +static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first, + unsigned int last) { struct target *target = bank->target; struct stm32x_flash_bank *stm32x_info = bank->driver_priv; @@ -545,6 +669,13 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last) return ERROR_TARGET_NOT_HALTED; } + if (stm32x_is_otp(bank)) { + if (!set) + return ERROR_COMMAND_ARGUMENT_INVALID; + + return stm32x_otp_protect(bank, first, last); + } + /* read protection settings */ int retval = stm32x_read_options(bank); if (retval != ERROR_OK) { @@ -552,7 +683,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last) return retval; } - for (int i = first; i <= last; i++) { + for (unsigned int i = first; i <= last; i++) { if (set) stm32x_info->option_bytes.protection &= ~(1 << i); else @@ -578,47 +709,15 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; - /* see contrib/loaders/flash/stm32f2x.S for src */ - static const uint8_t stm32x_flash_write_code[] = { - /* wait_fifo: */ - 0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */ - 0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */ - 0x1A, 0xD0, /* beq exit */ - 0x47, 0x68, /* ldr r7, [r0, #4] */ - 0x47, 0x45, /* cmp r7, r8 */ - 0xF7, 0xD0, /* beq wait_fifo */ - - 0xDF, 0xF8, 0x34, 0x60, /* ldr r6, STM32_PROG16 */ - 0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */ - 0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */ - 0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */ - 0xBF, 0xF3, 0x4F, 0x8F, /* dsb sy */ - /* busy: */ - 0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */ - 0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */ - 0xFB, 0xD1, /* bne busy */ - 0x16, 0xF0, 0xF0, 0x0F, /* tst r6, #0xf0 */ - 0x07, 0xD1, /* bne error */ - - 0x8F, 0x42, /* cmp r7, r1 */ - 0x28, 0xBF, /* it cs */ - 0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */ - 0x47, 0x60, /* str r7, [r0, #4] */ - 0x01, 0x3B, /* subs r3, r3, #1 */ - 0x13, 0xB1, /* cbz r3, exit */ - 0xDF, 0xE7, /* b wait_fifo */ - /* error: */ - 0x00, 0x21, /* movs r1, #0 */ - 0x41, 0x60, /* str r1, [r0, #4] */ - /* exit: */ - 0x30, 0x46, /* mov r0, r6 */ - 0x00, 0xBE, /* bkpt #0x00 */ - - /* : */ - 0x01, 0x01, 0x00, 0x00, /* .word 0x00000101 */ +#include "../../../contrib/loaders/flash/stm32/stm32f2x.inc" }; + if (stm32x_is_otp(bank) && !stm32x_is_otp_unlocked(bank)) { + LOG_ERROR("OTP memory bank is disabled for write commands."); + return ERROR_FAIL; + } + if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &write_algorithm) != ERROR_OK) { LOG_WARNING("no working area available, can't do block memory writes"); @@ -628,8 +727,10 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, retval = target_write_buffer(target, write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + target_free_working_area(target, write_algorithm); return retval; + } /* memory buffer */ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { @@ -675,7 +776,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer, LOG_ERROR("flash memory write protected"); if (error != 0) { - LOG_ERROR("flash write failed = %08" PRIx32, error); + LOG_ERROR("flash write failed = 0x%08" PRIx32, error); /* Clear but report errors */ target_write_u32(target, STM32_FLASH_SR, error); retval = ERROR_FAIL; @@ -793,31 +894,68 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer, return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); } -static int setup_sector(struct flash_bank *bank, int start, int num, int size) +static void setup_sector(struct flash_bank *bank, unsigned int i, + unsigned int size) +{ + assert(i < bank->num_sectors); + bank->sectors[i].offset = bank->size; + bank->sectors[i].size = size; + bank->size += bank->sectors[i].size; + LOG_DEBUG("sector %u: %ukBytes", i, size >> 10); +} + +static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb) { + if (i < 4) + return max_sector_size_in_kb / 8; + if (i == 4) + return max_sector_size_in_kb / 2; + return max_sector_size_in_kb; +} + +static unsigned int calculate_number_of_sectors(struct flash_bank *bank, + uint16_t flash_size_in_kb, + uint16_t max_sector_size_in_kb) +{ + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; + uint16_t remaining_flash_size_in_kb = flash_size_in_kb; + unsigned int nr_sectors; - for (int i = start; i < (start + num) ; i++) { - assert(i < bank->num_sectors); - bank->sectors[i].offset = bank->size; - bank->sectors[i].size = size; - bank->size += bank->sectors[i].size; - LOG_DEBUG("sector %d: %dkBytes", i, size >> 10); + /* Dual Bank Flash has two identically-arranged banks of sectors. */ + if (stm32x_info->has_large_mem) + remaining_flash_size_in_kb /= 2; + + for (nr_sectors = 0; remaining_flash_size_in_kb > 0; nr_sectors++) { + uint16_t size_in_kb = sector_size_in_kb(nr_sectors, max_sector_size_in_kb); + if (size_in_kb > remaining_flash_size_in_kb) { + LOG_INFO("%s Bank %" PRIu16 " kiB final sector clipped to %" PRIu16 " kiB", + stm32x_info->has_large_mem ? "Dual" : "Single", + flash_size_in_kb, remaining_flash_size_in_kb); + remaining_flash_size_in_kb = 0; + } else { + remaining_flash_size_in_kb -= size_in_kb; + } } - return start + num; + return stm32x_info->has_large_mem ? nr_sectors*2 : nr_sectors; } -static void setup_bank(struct flash_bank *bank, int start, +static void setup_bank(struct flash_bank *bank, unsigned int start, uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb) { - int remain; - - start = setup_sector(bank, start, 4, (max_sector_size_in_kb / 8) * 1024); - start = setup_sector(bank, start, 1, (max_sector_size_in_kb / 2) * 1024); - - /* remaining sectors all of size max_sector_size_in_kb */ - remain = (flash_size_in_kb / max_sector_size_in_kb) - 1; - start = setup_sector(bank, start, remain, max_sector_size_in_kb * 1024); + uint16_t remaining_flash_size_in_kb = flash_size_in_kb; + unsigned int sector_index = 0; + while (remaining_flash_size_in_kb > 0) { + uint16_t size_in_kb = sector_size_in_kb(sector_index, max_sector_size_in_kb); + if (size_in_kb > remaining_flash_size_in_kb) { + /* Clip last sector. Already warned in + * calculate_number_of_sectors. */ + size_in_kb = remaining_flash_size_in_kb; + } + setup_sector(bank, start + sector_index, size_in_kb * 1024); + remaining_flash_size_in_kb -= size_in_kb; + sector_index++; + } } static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) @@ -828,25 +966,17 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) * Only effects Rev A silicon */ struct target *target = bank->target; - uint32_t cpuid; /* read stm32 device id register */ int retval = target_read_u32(target, 0xE0042000, device_id); if (retval != ERROR_OK) return retval; - if ((*device_id & 0xfff) == 0x411) { - /* read CPUID reg to check core type */ - retval = target_read_u32(target, 0xE000ED00, &cpuid); - if (retval != ERROR_OK) - return retval; - - /* check for cortex_m4 */ - if (((cpuid >> 4) & 0xFFF) == 0xC24) { - *device_id &= ~((0xFFFF << 16) | 0xfff); - *device_id |= (0x1000 << 16) | 0x413; - LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE"); - } + if ((*device_id & 0xfff) == 0x411 + && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) { + *device_id &= ~((0xFFFF << 16) | 0xfff); + *device_id |= (0x1000 << 16) | 0x413; + LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE"); } return retval; } @@ -855,15 +985,17 @@ static int stm32x_probe(struct flash_bank *bank) { struct target *target = bank->target; struct stm32x_flash_bank *stm32x_info = bank->driver_priv; - int i, num_prot_blocks; + unsigned int num_prot_blocks, num_sectors; uint16_t flash_size_in_kb; + uint16_t otp_size_in_b; + uint16_t otp_sector_size; uint32_t flash_size_reg = 0x1FFF7A22; uint16_t max_sector_size_in_kb = 128; uint16_t max_flash_size_in_kb; uint32_t device_id; uint32_t base_address = 0x08000000; - stm32x_info->probed = 0; + stm32x_info->probed = false; stm32x_info->has_large_mem = false; stm32x_info->has_boot_addr = false; stm32x_info->has_extra_options = false; @@ -871,23 +1003,58 @@ static int stm32x_probe(struct flash_bank *bank) stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */ num_prot_blocks = 0; - if (bank->sectors) { - free(bank->sectors); - bank->num_sectors = 0; - bank->sectors = NULL; + free(bank->sectors); + bank->num_sectors = 0; + bank->sectors = NULL; + + free(bank->prot_blocks); + bank->num_prot_blocks = 0; + bank->prot_blocks = NULL; + + if (!target_was_examined(target)) { + LOG_ERROR("Target not examined yet"); + return ERROR_TARGET_NOT_EXAMINED; } - if (bank->prot_blocks) { - free(bank->prot_blocks); - bank->num_prot_blocks = 0; - bank->prot_blocks = NULL; + /* if explicitly called out as OTP bank, short circuit probe */ + if (stm32x_is_otp(bank)) { + if (stm32x_otp_is_f7(bank)) { + otp_size_in_b = STM32F7_OTP_SIZE; + otp_sector_size = STM32F7_OTP_SECTOR_SIZE; + } else { + otp_size_in_b = STM32F2_OTP_SIZE; + otp_sector_size = STM32F2_OTP_SECTOR_SIZE; + } + + num_sectors = otp_size_in_b / otp_sector_size; + LOG_INFO("flash size = %" PRIu16 " bytes", otp_size_in_b); + + assert(num_sectors > 0); + + bank->num_sectors = num_sectors; + bank->sectors = calloc(sizeof(struct flash_sector), num_sectors); + + if (stm32x_otp_is_f7(bank)) + bank->size = STM32F7_OTP_SIZE; + else + bank->size = STM32F2_OTP_SIZE; + + for (unsigned int i = 0; i < num_sectors; i++) { + bank->sectors[i].offset = i * otp_sector_size; + bank->sectors[i].size = otp_sector_size; + bank->sectors[i].is_erased = 1; + bank->sectors[i].is_protected = 0; + } + + stm32x_info->probed = true; + return ERROR_OK; } /* read stm32 device id register */ int retval = stm32x_get_device_id(bank, &device_id); if (retval != ERROR_OK) return retval; - LOG_INFO("device id = 0x%08" PRIx32 "", device_id); + LOG_INFO("device id = 0x%08" PRIx32, device_id); device_id &= 0xfff; /* only bits 0-11 are used further on */ /* set max flash size depending on family, id taken from AN2606 */ @@ -960,7 +1127,7 @@ static int stm32x_probe(struct flash_bank *bank) /* failed reading flash size or flash size invalid (early silicon), * default to max target family */ if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) { - LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash", + LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16 "k flash", max_flash_size_in_kb); flash_size_in_kb = max_flash_size_in_kb; } @@ -972,7 +1139,7 @@ static int stm32x_probe(struct flash_bank *bank) flash_size_in_kb = stm32x_info->user_bank_size / 1024; } - LOG_INFO("flash size = %dkbytes", flash_size_in_kb); + LOG_INFO("flash size = %" PRIu16 " kbytes", flash_size_in_kb); /* did we assign flash size? */ assert(flash_size_in_kb != 0xffff); @@ -987,10 +1154,10 @@ static int stm32x_probe(struct flash_bank *bank) } if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) { stm32x_info->has_large_mem = true; - LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb); + LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb); } else { stm32x_info->has_large_mem = false; - LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb); + LOG_INFO("Single Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb); } } @@ -1004,27 +1171,27 @@ static int stm32x_probe(struct flash_bank *bank) } if (optiondata & OPTCR_NDBANK) { stm32x_info->has_large_mem = false; - LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb); + LOG_INFO("Single Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb); } else { stm32x_info->has_large_mem = true; max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */ - LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb); + LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb); } } /* calculate numbers of pages */ - int num_pages = flash_size_in_kb / max_sector_size_in_kb - + (stm32x_info->has_large_mem ? 8 : 4); + unsigned int num_pages = calculate_number_of_sectors( + bank, flash_size_in_kb, max_sector_size_in_kb); bank->base = base_address; bank->num_sectors = num_pages; - bank->sectors = malloc(sizeof(struct flash_sector) * num_pages); - for (i = 0; i < num_pages; i++) { + bank->sectors = calloc(num_pages, sizeof(struct flash_sector)); + for (unsigned int i = 0; i < num_pages; i++) { bank->sectors[i].is_erased = -1; bank->sectors[i].is_protected = 0; } bank->size = 0; - LOG_DEBUG("allocated %d sectors", num_pages); + LOG_DEBUG("allocated %u sectors", num_pages); /* F76x/77x in dual bank mode */ if ((device_id == 0x451) && stm32x_info->has_large_mem) @@ -1032,9 +1199,9 @@ static int stm32x_probe(struct flash_bank *bank) if (num_prot_blocks) { bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks); - for (i = 0; i < num_prot_blocks; i++) + for (unsigned int i = 0; i < num_prot_blocks; i++) bank->prot_blocks[i].is_protected = 0; - LOG_DEBUG("allocated %d prot blocks", num_prot_blocks); + LOG_DEBUG("allocated %u prot blocks", num_prot_blocks); } if (stm32x_info->has_large_mem) { @@ -1045,9 +1212,10 @@ static int stm32x_probe(struct flash_bank *bank) /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */ if (device_id == 0x451) { - for (i = 0; i < num_prot_blocks; i++) { + for (unsigned int i = 0; i < num_prot_blocks; i++) { bank->prot_blocks[i].offset = bank->sectors[i << 1].offset; - bank->prot_blocks[i].size = bank->sectors[i << 1].size << 1; + bank->prot_blocks[i].size = bank->sectors[i << 1].size + + bank->sectors[(i << 1) + 1].size; } } } else { @@ -1056,7 +1224,7 @@ static int stm32x_probe(struct flash_bank *bank) /* F413/F423, sectors 14 and 15 share one common protection bit */ if (device_id == 0x463) { - for (i = 0; i < num_prot_blocks; i++) { + for (unsigned int i = 0; i < num_prot_blocks; i++) { bank->prot_blocks[i].offset = bank->sectors[i].offset; bank->prot_blocks[i].size = bank->sectors[i].size; } @@ -1066,7 +1234,7 @@ static int stm32x_probe(struct flash_bank *bank) bank->num_prot_blocks = num_prot_blocks; assert((bank->size >> 10) == flash_size_in_kb); - stm32x_info->probed = 1; + stm32x_info->probed = true; return ERROR_OK; } @@ -1078,7 +1246,7 @@ static int stm32x_auto_probe(struct flash_bank *bank) return stm32x_probe(bank); } -static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) +static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd) { uint32_t dbgmcu_idcode; @@ -1216,6 +1384,9 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) case 0x1000: rev_str = "A"; break; + case 0x1001: + rev_str = "Z"; + break; } break; @@ -1240,14 +1411,14 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) break; default: - snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n"); + command_print_sameline(cmd, "Cannot identify target as a STM32F2/4/7\n"); return ERROR_FAIL; } - if (rev_str != NULL) - snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str); + if (rev_str) + command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str); else - snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id); + command_print_sameline(cmd, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id); return ERROR_OK; } @@ -1262,7 +1433,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1274,7 +1445,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) } if (stm32x_read_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "%s failed to read options", bank->driver->name); + command_print(CMD, "%s failed to read options", bank->driver->name); return ERROR_OK; } @@ -1282,11 +1453,11 @@ COMMAND_HANDLER(stm32x_handle_lock_command) stm32x_info->option_bytes.RDP = 0; if (stm32x_write_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "%s failed to lock device", bank->driver->name); + command_print(CMD, "%s failed to lock device", bank->driver->name); return ERROR_OK; } - command_print(CMD_CTX, "%s locked", bank->driver->name); + command_print(CMD, "%s locked", bank->driver->name); return ERROR_OK; } @@ -1301,7 +1472,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1313,7 +1484,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) } if (stm32x_read_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "%s failed to read options", bank->driver->name); + command_print(CMD, "%s failed to read options", bank->driver->name); return ERROR_OK; } @@ -1321,15 +1492,15 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) * this will also force a device unlock if set */ stm32x_info->option_bytes.RDP = 0xAA; if (stm32x_info->has_optcr2_pcrop) { - stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors); + stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1U << bank->num_sectors); } if (stm32x_write_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name); + command_print(CMD, "%s failed to unlock device", bank->driver->name); return ERROR_OK; } - command_print(CMD_CTX, "%s unlocked.\n" + command_print(CMD, "%s unlocked.\n" "INFO: a reset or power cycle is required " "for the new settings to take effect.", bank->driver->name); @@ -1381,27 +1552,21 @@ static int stm32x_mass_erase(struct flash_bank *bank) COMMAND_HANDLER(stm32x_handle_mass_erase_command) { - int i; - if (CMD_ARGC < 1) { - command_print(CMD_CTX, "stm32x mass_erase "); + command_print(CMD, "stm32x mass_erase "); return ERROR_COMMAND_SYNTAX_ERROR; } struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_mass_erase(bank); if (retval == ERROR_OK) { - /* set all sectors as erased */ - for (i = 0; i < bank->num_sectors; i++) - bank->sectors[i].is_erased = 1; - - command_print(CMD_CTX, "stm32x mass erase complete"); + command_print(CMD, "stm32x mass erase complete"); } else { - command_print(CMD_CTX, "stm32x mass erase failed"); + command_print(CMD, "stm32x mass erase failed"); } return retval; @@ -1414,16 +1579,16 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command) struct stm32x_flash_bank *stm32x_info = NULL; if (CMD_ARGC != 1) { - command_print(CMD_CTX, "stm32f2x options_read "); + command_print(CMD, "stm32f2x options_read "); return ERROR_COMMAND_SYNTAX_ERROR; } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1431,20 +1596,20 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command) if (stm32x_info->has_boot_addr) { uint32_t boot_addr = stm32x_info->option_bytes.boot_addr; - command_print(CMD_CTX, "stm32f2x user_options 0x%03X," - " boot_add0 0x%04X, boot_add1 0x%04X", + command_print(CMD, "stm32f2x user_options 0x%03" PRIX16 "," + " boot_add0 0x%04" PRIX32 ", boot_add1 0x%04" PRIX32, stm32x_info->option_bytes.user_options, boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16); if (stm32x_info->has_optcr2_pcrop) { - command_print(CMD_CTX, "stm32f2x optcr2_pcrop 0x%08X", + command_print(CMD, "stm32f2x optcr2_pcrop 0x%08" PRIX32, stm32x_info->option_bytes.optcr2_pcrop); } } else { - command_print(CMD_CTX, "stm32f2x user_options 0x%03X", + command_print(CMD, "stm32f2x user_options 0x%03" PRIX16, stm32x_info->option_bytes.user_options); } } else { - command_print(CMD_CTX, "stm32f2x user_options 0x%02X", + command_print(CMD, "stm32f2x user_options 0x%02" PRIX16, stm32x_info->option_bytes.user_options); } @@ -1460,22 +1625,22 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) uint16_t user_options, boot_addr0, boot_addr1, options_mask; if (CMD_ARGC < 1) { - command_print(CMD_CTX, "stm32f2x options_write ..."); + command_print(CMD, "stm32f2x options_write ..."); return ERROR_COMMAND_SYNTAX_ERROR; } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; if (stm32x_info->has_boot_addr) { if (CMD_ARGC != 4) { - command_print(CMD_CTX, "stm32f2x options_write " + command_print(CMD, "stm32f2x options_write " " "); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1484,7 +1649,7 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16); } else { if (CMD_ARGC != 2) { - command_print(CMD_CTX, "stm32f2x options_write "); + command_print(CMD, "stm32f2x options_write "); return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -1493,22 +1658,22 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) options_mask = !stm32x_info->has_extra_options ? ~0xfc : ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc); if (user_options & options_mask) { - command_print(CMD_CTX, "stm32f2x invalid user_options"); + command_print(CMD, "stm32f2x invalid user_options"); return ERROR_COMMAND_ARGUMENT_INVALID; } stm32x_info->option_bytes.user_options = user_options; if (stm32x_write_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "stm32f2x failed to write options"); + command_print(CMD, "stm32f2x failed to write options"); return ERROR_OK; } /* switching between single- and dual-bank modes requires re-probe */ /* ... and reprogramming of whole flash */ - stm32x_info->probed = 0; + stm32x_info->probed = false; - command_print(CMD_CTX, "stm32f2x write options complete.\n" + command_print(CMD, "stm32f2x write options complete.\n" "INFO: a reset or power cycle is required " "for the new settings to take effect."); return retval; @@ -1522,41 +1687,72 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command) uint32_t optcr2_pcrop; if (CMD_ARGC != 2) { - command_print(CMD_CTX, "stm32f2x optcr2_write "); + command_print(CMD, "stm32f2x optcr2_write "); return ERROR_COMMAND_SYNTAX_ERROR; } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; if (!stm32x_info->has_optcr2_pcrop) { - command_print(CMD_CTX, "no optcr2 register"); + command_print(CMD, "no optcr2 register"); return ERROR_COMMAND_ARGUMENT_INVALID; } - command_print(CMD_CTX, "INFO: To disable PCROP, set PCROP_RDP" + command_print(CMD, "INFO: To disable PCROP, set PCROP_RDP" " with PCROPi bits STILL SET, then\nlock device and" " finally unlock it. Clears PCROP and mass erases flash."); retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop); stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop; if (stm32x_write_options(bank) != ERROR_OK) { - command_print(CMD_CTX, "stm32f2x failed to write options"); + command_print(CMD, "stm32f2x failed to write options"); return ERROR_OK; } - command_print(CMD_CTX, "stm32f2x optcr2_write complete."); + command_print(CMD, "stm32f2x optcr2_write complete."); + return retval; +} + +COMMAND_HANDLER(stm32x_handle_otp_command) +{ + if (CMD_ARGC < 2) { + command_print(CMD, "stm32x otp (enable|disable|show)"); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + struct flash_bank *bank; + int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); + if (retval != ERROR_OK) + return retval; + if (stm32x_is_otp(bank)) { + if (strcmp(CMD_ARGV[1], "enable") == 0) { + stm32x_otp_enable(bank); + } else if (strcmp(CMD_ARGV[1], "disable") == 0) { + stm32x_otp_disable(bank); + } else if (strcmp(CMD_ARGV[1], "show") == 0) { + command_print(CMD, + "OTP memory bank #%u is %s for write commands.", + bank->bank_number, + stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled"); + } else { + return ERROR_COMMAND_SYNTAX_ERROR; + } + } else { + command_print(CMD, "Failed: not an OTP bank."); + } + return retval; } -static const struct command_registration stm32x_exec_command_handlers[] = { +static const struct command_registration stm32f2x_exec_command_handlers[] = { { .name = "lock", .handler = stm32x_handle_lock_command, @@ -1599,24 +1795,30 @@ static const struct command_registration stm32x_exec_command_handlers[] = { .usage = "bank_id optcr2", .help = "Write optcr2 word", }, - + { + .name = "otp", + .handler = stm32x_handle_otp_command, + .mode = COMMAND_EXEC, + .usage = "bank_id", + .help = "OTP (One Time Programmable) memory write enable/disable.", + }, COMMAND_REGISTRATION_DONE }; -static const struct command_registration stm32x_command_handlers[] = { +static const struct command_registration stm32f2x_command_handlers[] = { { .name = "stm32f2x", .mode = COMMAND_ANY, .help = "stm32f2x flash command group", .usage = "", - .chain = stm32x_exec_command_handlers, + .chain = stm32f2x_exec_command_handlers, }, COMMAND_REGISTRATION_DONE }; -struct flash_driver stm32f2x_flash = { +const struct flash_driver stm32f2x_flash = { .name = "stm32f2x", - .commands = stm32x_command_handlers, + .commands = stm32f2x_command_handlers, .flash_bank_command = stm32x_flash_bank_command, .erase = stm32x_erase, .protect = stm32x_protect, @@ -1627,4 +1829,5 @@ struct flash_driver stm32f2x_flash = { .erase_check = default_flash_blank_check, .protect_check = stm32x_protect_check, .info = get_stm32x_info, + .free_driver_priv = default_flash_free_driver_priv, };