X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fz80.src%2Fz80.cc;h=46c5654d2675e04027564b8e8d988fea87d30317;hb=90f4aedaef8a2310573eef905f95c671f84e5cde;hp=e0b1b12392bffec99775efffc5504d9eca7c8770;hpb=8c8f34ff4281a55d2f535335c02999246e9e12f2;p=fw%2Fsdcc diff --git a/sim/ucsim/z80.src/z80.cc b/sim/ucsim/z80.src/z80.cc index e0b1b123..46c5654d 100644 --- a/sim/ucsim/z80.src/z80.cc +++ b/sim/ucsim/z80.src/z80.cc @@ -48,7 +48,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define uint32 t_addr #define uint8 unsigned char -#define int8 char /*******************************************************************/ @@ -68,7 +67,7 @@ cl_z80::init(void) { cl_uc::init(); /* Memories now exist */ - rom= mem(MEM_ROM); + rom= address_space(MEM_ROM_ID); // ram= mem(MEM_XRAM); ram= rom; @@ -90,7 +89,7 @@ cl_z80::id_string(void) /* * Making elements of the controller */ - +/* t_addr cl_z80::get_mem_size(enum mem_class type) { @@ -102,6 +101,7 @@ cl_z80::get_mem_size(enum mem_class type) } return(cl_uc::get_mem_size(type)); } +*/ void cl_z80::mk_hw_elements(void) @@ -110,6 +110,27 @@ cl_z80::mk_hw_elements(void) /* t_uc::mk_hw() does nothing */ } +void +cl_z80::make_memories(void) +{ + class cl_address_space *as; + + as= new cl_address_space("rom", 0, 0x10000, 8); + as->init(); + address_spaces->add(as); + + class cl_address_decoder *ad; + class cl_memory_chip *chip; + + chip= new cl_memory_chip("rom_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); +} + /* * Help command interpreter @@ -177,12 +198,12 @@ cl_z80::get_disasm_info(t_addr addr, int start_addr = addr; struct dis_entry *dis_e; - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); dis_e = NULL; switch(code) { case 0xcb: /* ESC code to lots of op-codes, all 2-byte */ - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); i= 0; while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code && disass_z80_cb[i].mnemonic) @@ -194,7 +215,7 @@ cl_z80::get_disasm_info(t_addr addr, break; case 0xed: /* ESC code to about 80 opcodes of various lengths */ - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); i= 0; while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code && disass_z80_ed[i].mnemonic) @@ -206,11 +227,11 @@ cl_z80::get_disasm_info(t_addr addr, break; case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */ - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); if (code == 0xcb) { immed_n = 2; addr++; // pass up immed data - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); i= 0; while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code && disass_z80_ddcb[i].mnemonic) @@ -232,11 +253,11 @@ cl_z80::get_disasm_info(t_addr addr, break; case 0xfd: /* ESC codes,sme as dd but IY centric */ - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); if (code == 0xcb) { immed_n = 2; addr++; // pass up immed data - code= get_mem(MEM_ROM, addr++); + code= get_mem(MEM_ROM_ID, addr++); i= 0; while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code && disass_z80_fdcb[i].mnemonic) @@ -310,35 +331,35 @@ cl_z80::disass(t_addr addr, char *sep) while (*b) { if (*b == '%') - { - b++; - switch (*(b++)) - { - case 'd': // d jump relative target, signed? byte immediate operand - sprintf(temp, "#%d", (char)get_mem(MEM_ROM, addr+immed_offset)); - ++immed_offset; - break; - case 'w': // w word immediate operand - sprintf(temp, "#0x%04x", - (uint)((get_mem(MEM_ROM, addr+immed_offset)) | - (get_mem(MEM_ROM, addr+immed_offset+1)<<8)) ); - ++immed_offset; - ++immed_offset; - break; - case 'b': // b byte immediate operand - sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM, addr+immed_offset)); - ++immed_offset; - break; - default: - strcpy(temp, "?"); - break; - } - t= temp; - while (*t) - *(p++)= *(t++); - } + { + b++; + switch (*(b++)) + { + case 'd': // d jump relative target, signed? byte immediate operand + sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset)); + ++immed_offset; + break; + case 'w': // w word immediate operand + sprintf(temp, "#0x%04x", + (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) | + (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) ); + ++immed_offset; + ++immed_offset; + break; + case 'b': // b byte immediate operand + sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset)); + ++immed_offset; + break; + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } else - *(p++)= *(b++); + *(p++)= *(b++); } *p= '\0'; @@ -359,7 +380,7 @@ cl_z80::disass(t_addr addr, char *sep) if (sep == NULL) { while (strlen(buf) < 6) - strcat(buf, " "); + strcat(buf, " "); } else strcat(buf, sep); @@ -369,36 +390,36 @@ cl_z80::disass(t_addr addr, char *sep) void -cl_z80::print_regs(class cl_console *con) +cl_z80::print_regs(class cl_console_base *con) { con->dd_printf("SZ-A--P-C Flags= 0x%02x %3d %c ", - regs.F, regs.F, isprint(regs.F)?regs.F:'.'); + regs.F, regs.F, isprint(regs.F)?regs.F:'.'); con->dd_printf("A= 0x%02x %3d %c\n", - regs.A, regs.A, isprint(regs.A)?regs.A:'.'); + regs.A, regs.A, isprint(regs.A)?regs.A:'.'); con->dd_printf("%c%c-%c--%c-%c\n", - (regs.F&BIT_S)?'1':'0', - (regs.F&BIT_Z)?'1':'0', - (regs.F&BIT_A)?'1':'0', - (regs.F&BIT_P)?'1':'0', - (regs.F&BIT_C)?'1':'0'); + (regs.F&BIT_S)?'1':'0', + (regs.F&BIT_Z)?'1':'0', + (regs.F&BIT_A)?'1':'0', + (regs.F&BIT_P)?'1':'0', + (regs.F&BIT_C)?'1':'0'); con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ", - regs.BC, ram->get(regs.BC), ram->get(regs.BC), - isprint(ram->get(regs.BC))?ram->get(regs.BC):'.'); + regs.BC, ram->get(regs.BC), ram->get(regs.BC), + isprint(ram->get(regs.BC))?ram->get(regs.BC):'.'); con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ", - regs.DE, ram->get(regs.DE), ram->get(regs.DE), - isprint(ram->get(regs.DE))?ram->get(regs.DE):'.'); + regs.DE, ram->get(regs.DE), ram->get(regs.DE), + isprint(ram->get(regs.DE))?ram->get(regs.DE):'.'); con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n", - regs.HL, ram->get(regs.HL), ram->get(regs.HL), - isprint(ram->get(regs.HL))?ram->get(regs.HL):'.'); + regs.HL, ram->get(regs.HL), ram->get(regs.HL), + isprint(ram->get(regs.HL))?ram->get(regs.HL):'.'); con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ", - regs.IX, ram->get(regs.IX), ram->get(regs.IX), - isprint(ram->get(regs.IX))?ram->get(regs.IX):'.'); + regs.IX, ram->get(regs.IX), ram->get(regs.IX), + isprint(ram->get(regs.IX))?ram->get(regs.IX):'.'); con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ", - regs.IY, ram->get(regs.IY), ram->get(regs.IY), - isprint(ram->get(regs.IY))?ram->get(regs.IY):'.'); + regs.IY, ram->get(regs.IY), ram->get(regs.IY), + isprint(ram->get(regs.IY))?ram->get(regs.IY):'.'); con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n", - regs.SP, ram->get(regs.SP), ram->get(regs.SP), - isprint(ram->get(regs.SP))?ram->get(regs.SP):'.'); + regs.SP, ram->get(regs.SP), ram->get(regs.SP), + isprint(ram->get(regs.SP))?ram->get(regs.SP):'.'); print_disass(PC, con); } @@ -593,10 +614,11 @@ cl_z80::exec_inst(void) case 0xff: return(inst_rst(code)); } - if (PC) + /*if (PC) PC--; else - PC= get_mem_size(MEM_ROM)-1; + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); sim->stop(resINV_INST); return(resINV_INST);