X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fz80.src%2Finst_ed.cc;fp=sim%2Fucsim%2Fz80.src%2Finst_ed.cc;h=06874605c9feb91338decd055526c7c865c34a5b;hb=b49b8f5a2e8ac5cea3beb6e503159dd3d09f6728;hp=a91524f8b0a10e4dd7855279277d56ce63122207;hpb=2109a06030f5d8dcb7412a67cf61315e6f69a427;p=fw%2Fsdcc

diff --git a/sim/ucsim/z80.src/inst_ed.cc b/sim/ucsim/z80.src/inst_ed.cc
index a91524f8..06874605 100644
--- a/sim/ucsim/z80.src/inst_ed.cc
+++ b/sim/ucsim/z80.src/inst_ed.cc
@@ -271,18 +271,24 @@ cl_z80::inst_ed(void)
     return(resGO);
 
     case 0xB1: // CPIR
-/* fixme: checkme, compare to other emul. */
       // compare acc with mem(HL), if ACC=0 set Z flag.  Incr HL, decr BC.
-      regs.F &= ~(BIT_ALL);  /* clear these */
-      regs.F |= BIT_N | BIT_P;
+      regs.F &= ~(BIT_P | BIT_A | BIT_Z | BIT_S);  /* clear these */
+      regs.F |= BIT_N;
       do {
-        if ((regs.A - get1(regs.HL)) == 0) {
-          regs.F |= (BIT_Z | BIT_P);
-          return(resGO);
-        }
+        if((regs.A - get1(regs.HL)) == 0)
+          regs.F |= BIT_Z;
+        else
+          regs.F &= ~BIT_Z;
+        if((regs.A - get1(regs.HL)) & 0x80)
+          regs.F |= BIT_S;
+        else
+          regs.F &= ~BIT_S;
+/* fixme: set BIT_A correctly. */
         ++regs.HL;
         --regs.BC;
-      } while (regs.BC != 0);
+      } while (regs.BC != 0 && (regs.F & BIT_Z) == 0);
+      if(regs.BC != 0)
+        regs.F |= BIT_P;
 
     return(resGO);
 #if 0