X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fstypes.h;h=f7380609495b3c3546231f9185f72a29bed29310;hb=b49b8f5a2e8ac5cea3beb6e503159dd3d09f6728;hp=81a50689e60658f34ac4402370eb28488596e757;hpb=f27cbdc6513b26748661452e50ed3af99fac16a2;p=fw%2Fsdcc diff --git a/sim/ucsim/stypes.h b/sim/ucsim/stypes.h index 81a50689..f7380609 100644 --- a/sim/ucsim/stypes.h +++ b/sim/ucsim/stypes.h @@ -31,16 +31,23 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #include "ddconfig.h" -typedef unsigned char uchar; -typedef unsigned int uint; -typedef unsigned long ulong; -typedef unsigned long t_addr; -typedef unsigned long t_mem; +typedef unsigned char uchar; +typedef unsigned int uint; +typedef unsigned long ulong; +typedef TYPE_DWORD t_addr; /* 32 bit max */ +typedef TYPE_UWORD t_mem; /* 16 bit max */ +typedef TYPE_WORD t_smem; /* signed 16 bit memory */ struct id_element { int id; - char *id_string; + const char *id_string; +}; + +enum error_type { + err_unknown = 0x01, + err_error = 0x02, + err_warning = 0x04 }; // table of dissassembled instructions @@ -49,21 +56,21 @@ struct dis_entry uint code, mask; char branch; uchar length; - char *mnemonic; + const char *mnemonic; }; // table entry of SFR and BIT names struct name_entry { - int cpu_type; - uint addr; - char *name; + int cpu_type; + t_addr addr; + const char *name; }; struct cpu_entry { - char *type_str; + const char *type_str; int type; int technology; }; @@ -75,8 +82,10 @@ struct cpu_entry #define CPU_51R 0x0010 #define CPU_89C51R 0x0020 #define CPU_251 0x0040 +#define CPU_DS390 0x0080 +#define CPU_DS390F 0x0100 #define CPU_ALL_51 (CPU_51|CPU_31) -#define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251) +#define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|CPU_DS390|CPU_DS390F) #define CPU_AVR 0x0001 #define CPU_ALL_AVR (CPU_AVR) @@ -84,6 +93,12 @@ struct cpu_entry #define CPU_Z80 0x0001 #define CPU_ALL_Z80 (CPU_Z80) +#define CPU_XA 0x0001 +#define CPU_ALL_XA (CPU_XA) + +#define CPU_HC08 0x0001 +#define CPU_ALL_HC08 (CPU_HC08) + #define CPU_CMOS 0x0001 #define CPU_HMOS 0x0002 @@ -94,15 +109,16 @@ enum mem_class MEM_XRAM, MEM_IRAM, MEM_SFR, + MEM_DUMMY, + MEM_IXRAM, MEM_TYPES }; -// Flags of consoles -#define CONS_NONE 0 -#define CONS_DEBUG 0x01 // Print debug messages on this console -#define CONS_FROZEN 0x02 // Console is frozen (g command issued) -#define CONS_PROMPT 0x04 // Prompt is out, waiting for input -#define CONS_INTERACTIVE 0x08 // Interactive console +#define MEM_ROM_ID "rom" +#define MEM_SFR_ID "sfr" +#define MEM_XRAM_ID "xram" +#define MEM_IXRAM_ID "ixram" +#define MEM_IRAM_ID "iram" // States of simulator #define SIM_NONE 0 @@ -125,30 +141,18 @@ enum mem_class #define resBREAKPOINT 104 /* Breakpoint */ #define resUSER 105 /* Stopped by user */ #define resINV_INST 106 /* Invalid instruction */ - +#define resBITADDR 107 /* Bit address is uninterpretable */ +#define resERROR 108 /* Error happened during instruction exec */ #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07)) -#define SET_BIT(newbit, reg, bitmask) \ -if (newbit) \ - (mem(MEM_SFR))->set_bit1((reg), (bitmask)); \ -else \ - (mem(MEM_SFR))->set_bit0((reg), (bitmask)); -#define SFR_SET_BIT(newbit, reg, bitmask) \ -if (newbit) \ - sfr->set_bit1((reg), (bitmask)); \ -else \ - sfr->set_bit0((reg), (bitmask)); -#define GET_C (get_mem(MEM_SFR, PSW) & bmCY) -#define SFR_GET_C (sfr->get(PSW) & bmCY) -#define SET_C(newC) SET_BIT((newC), PSW, bmCY) - -#define IRAM_SIZE 256 /* Size of Internal RAM */ -#define SFR_SIZE 256 /* Size of SFR area */ -#define SFR_START 128 /* Start address of SFR area */ -#define ERAM_SIZE 256 /* Size of ERAM in 51R */ -#define XRAM_SIZE 0x10000 /* Size of External RAM */ + +//#define IRAM_SIZE 256 /* Size of Internal RAM */ +//#define SFR_SIZE 256 /* Size of SFR area */ +//#define SFR_START 128 /* Start address of SFR area */ +//#define ERAM_SIZE 256 /* Size of ERAM in 51R */ +//#define XRAM_SIZE 0x10000 /* Size of External RAM */ //#define IROM_SIZE 0x1000 /* Size of Internal ROM */ -#define EROM_SIZE 0x10000 /* Size of External ROM */ +//#define EROM_SIZE 0x10000 /* Size of External ROM */ /* Type of breakpoints */ @@ -173,19 +177,22 @@ enum brk_event brkWIRAM, /* wi */ brkRIRAM, /* ri */ brkWSFR, /* ws */ - brkRSFR /* rs */ + brkRSFR, /* rs */ + brkREAD, + brkWRITE, + brkACCESS }; -struct event_rec -{ - t_addr wx; /* write to XRAM at this address, else -1 */ - t_addr rx; /* read from XRAM at this address, else -1 */ - t_addr wi; /* write to IRAM at this address, else -1 */ - t_addr ri; /* read from IRAM at this address, else -1 */ - t_addr ws; /* write to SFR at this address, else -1 */ - t_addr rs; /* read from SFR at this address, else -1 */ - t_addr rc; /* read from ROM at this address, else -1 */ -}; +//struct event_rec +//{ +// t_addr wx; /* write to XRAM at this address, else -1 */ +// t_addr rx; /* read from XRAM at this address, else -1 */ +// t_addr wi; /* write to IRAM at this address, else -1 */ +// t_addr ri; /* read from IRAM at this address, else -1 */ +// t_addr ws; /* write to SFR at this address, else -1 */ +// t_addr rs; /* read from SFR at this address, else -1 */ +// t_addr rc; /* read from ROM at this address, else -1 */ +//}; /* Interrupt levels */ //#define IT_NO -1 /* not in interroupt service */ @@ -194,12 +201,20 @@ struct event_rec /* cathegories of hw elements (peripherials) */ enum hw_cath { - HW_TIMER, - HW_UART, - HW_PORT, - HW_PCA, - HW_INTERRUPT, - HW_WDT + HW_DUMMY = 0x0000, + HW_TIMER = 0x0002, + HW_UART = 0x0004, + HW_PORT = 0x0008, + HW_PCA = 0x0010, + HW_INTERRUPT = 0x0020, + HW_WDT = 0x0040 +}; + +// Events that can happen in peripherals +enum hw_event { + EV_OVERFLOW, + EV_PORT_CHANGED, + EV_T2_MODE_CHANGED }; // flags of hw units @@ -209,6 +224,14 @@ enum hw_cath { #define HWF_MISC 0x0004 +/* Letter cases */ +enum letter_case { + case_upper, /* all is upper case */ + case_lower, /* all is lower case */ + case_case /* first letter is upper, others are lower case */ +}; + + #endif /* End of stypes.h */