X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fs51.src%2Fuc390hw.cc;h=5012d676f15f1b04710637a982c32d147797de65;hb=90f4aedaef8a2310573eef905f95c671f84e5cde;hp=d8bae3600d8dbeb75bb268dc672f5df1f070d696;hpb=8c8f34ff4281a55d2f535335c02999246e9e12f2;p=fw%2Fsdcc diff --git a/sim/ucsim/s51.src/uc390hw.cc b/sim/ucsim/s51.src/uc390hw.cc index d8bae360..5012d676 100644 --- a/sim/ucsim/s51.src/uc390hw.cc +++ b/sim/ucsim/s51.src/uc390hw.cc @@ -39,15 +39,13 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA cl_uc390_hw::cl_uc390_hw (class cl_uc *auc): cl_hw (auc, HW_DUMMY, 0, "ds390hw") { - uc390 = (class t_uc390 *) uc; + uc390 = (class cl_uc390 *) uc; } int cl_uc390_hw::init(void) { - class cl_mem *sfr; - - sfr = uc->mem (MEM_SFR); + sfr = uc->address_space(MEM_SFR_ID); if (sfr) { /*cell_dps = sfr->register_hw (DPS , this, 0); @@ -89,22 +87,22 @@ cl_uc390_hw::init(void) } t_mem -cl_uc390_hw::read (class cl_cell *cell) +cl_uc390_hw::read (class cl_memory_cell *cell) { if (cell == cell_exif) { if (ctm_ticks && uc390->ticks->ticks >= ctm_ticks + 65535) - { - ctm_ticks = 0; - cell->set (cell->get() | 0x08); /* set CKRDY */ - } + { + ctm_ticks = 0; + cell->set (cell->get() | 0x08); /* set CKRDY */ + } } return cell->get(); } void -cl_uc390_hw::write (class cl_cell *cell, t_mem *val) +cl_uc390_hw::write (class cl_memory_cell *cell, t_mem *val) { if (cell == cell_dps) *val = (*val & 0xe5) | 0x04; @@ -113,7 +111,7 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) /* Bit 0 (BGS) is TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = (*val & ~0x01) | (cell_exif->get() & 0x01); + *val = (*val & ~0x01) | (cell_exif->get() & 0x01); /* CKRDY and RGMD are read-only */ *val = (*val & 0x0c) | (*val & ~0x0c); @@ -133,12 +131,12 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles *val = cell_acon->get(); else - { + { - /* lockout: IDM1:IDM0 and SA can't be set at the same time */ - if ((cell_mcon->get() & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */ - *val &= ~0x04; /* lockout SA */ - } + /* lockout: IDM1:IDM0 and SA can't be set at the same time */ + if ((cell_mcon->get() & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */ + *val &= ~0x04; /* lockout SA */ + } *val |= 0xf8; /* always 1 */ } else if (cell == cell_p5cnt) @@ -146,22 +144,22 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) /* Bits 0...2 are TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = (*val & ~0x07) | (cell_p5cnt->get() & 0x07); + *val = (*val & ~0x07) | (cell_p5cnt->get() & 0x07); } else if (cell == cell_c0c) { /* Bit 3 (CRST) is TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = (*val & ~0x08) | (cell_c0c->get() & 0x08); + *val = (*val & ~0x08) | (cell_c0c->get() & 0x08); } else if (cell == cell_pmr) { /* fixme: check previous state */ if ((*val & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */ { - ctm_ticks = uc390->ticks->ticks; - cell_exif->set (cell_exif->get() & ~0x08); /* clear CKRDY */ + ctm_ticks = uc390->ticks->ticks; + cell_exif->set (cell_exif->get() & ~0x08); /* clear CKRDY */ } else ctm_ticks = 0; @@ -172,7 +170,7 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) /* MCON is TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = cell_mcon->get(); + *val = cell_mcon->get(); else /* lockout: IDM1:IDM0 and SA can't be set at the same time */ if ((cell_acon->get() & 0x04) == 0x04) /* SA set? */ @@ -201,7 +199,7 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) /* COR is TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = cell_cor->get(); + *val = cell_cor->get(); } else if (cell == cell_mcnt0) { @@ -228,42 +226,42 @@ cl_uc390_hw::write (class cl_cell *cell, t_mem *val) /* Bits 0, 1, 3 and 6 are TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = (*val & ~0x4b) | (cell_wdcon->get() & 0x4b); + *val = (*val & ~0x4b) | (cell_wdcon->get() & 0x4b); } else if (cell == cell_c1c) { /* Bit 3 (CRST) is TA-protected */ if (timed_access_state != 2 || timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles - *val = (*val & ~0x08) | (cell_c1c->get() & 0x08); + *val = (*val & ~0x08) | (cell_c1c->get() & 0x08); } } /*void -cl_uc390_hw::mem_cell_changed (class cl_mem *mem, t_addr addr) +cl_uc390_hw::mem_cell_changed (class cl_m *mem, t_addr addr) { - class cl_mem *sfr = uc->mem (MEM_SFR); + class cl_m *sfr = uc->mem (MEM_SFR); if (mem && sfr && mem == sfr) switch (addr) { - case DPS: cell_dps = sfr->get_cell (DPS); break; - case P4CNT: cell_p4cnt = sfr->get_cell (P4CNT); break; - case EXIF: cell_exif = sfr->get_cell (EXIF); break; - case ACON: cell_acon = sfr->get_cell (ACON); break; - case P5CNT: cell_p5cnt = sfr->get_cell (P5CNT); break; - case C0C: cell_c0c = sfr->get_cell (C0C); break; - case PMR: cell_pmr = sfr->get_cell (PMR); break; - case MCON: cell_mcon = sfr->get_cell (MCON); break; - case TA: cell_ta = sfr->get_cell (TA); break; - case COR: cell_cor = sfr->get_cell (COR); break; - case MCNT0: cell_mcnt0 = sfr->get_cell (MCNT0); break; - case MCNT1: cell_mcnt1 = sfr->get_cell (MCNT1); break; - case MA: cell_ma = sfr->get_cell (MA); break; - case MB: cell_mb = sfr->get_cell (MB); break; - case MC: cell_mc = sfr->get_cell (MC); break; - case WDCON: cell_wdcon = sfr->get_cell (WDCON); break; - case C1C: cell_c1c = sfr->get_cell (C1C); break; + case DPS: cell_dps = sfr->get_cell (DPS); break; + case P4CNT: cell_p4cnt = sfr->get_cell (P4CNT); break; + case EXIF: cell_exif = sfr->get_cell (EXIF); break; + case ACON: cell_acon = sfr->get_cell (ACON); break; + case P5CNT: cell_p5cnt = sfr->get_cell (P5CNT); break; + case C0C: cell_c0c = sfr->get_cell (C0C); break; + case PMR: cell_pmr = sfr->get_cell (PMR); break; + case MCON: cell_mcon = sfr->get_cell (MCON); break; + case TA: cell_ta = sfr->get_cell (TA); break; + case COR: cell_cor = sfr->get_cell (COR); break; + case MCNT0: cell_mcnt0 = sfr->get_cell (MCNT0); break; + case MCNT1: cell_mcnt1 = sfr->get_cell (MCNT1); break; + case MA: cell_ma = sfr->get_cell (MA); break; + case MB: cell_mb = sfr->get_cell (MB); break; + case MC: cell_mc = sfr->get_cell (MC); break; + case WDCON: cell_wdcon = sfr->get_cell (WDCON); break; + case C1C: cell_c1c = sfr->get_cell (C1C); break; } }*/ @@ -275,16 +273,16 @@ cl_uc390_hw::reset(void) } void -cl_uc390_hw::print_info(class cl_console *con) +cl_uc390_hw::print_info(class cl_console_base *con) { int i; long l; - i = uc->get_mem (MEM_SFR, EXIF); + i = sfr->get (EXIF); con->dd_printf ("%s" " EXIF 0x%02x: IE5 %c IE4 %c IE3 %c IE2 %c CKRDY %c RGMD %c RGSL %c BGS %c\n", id_string, - i, + i, (i & 0x80) ? '1' : '0', (i & 0x40) ? '1' : '0', (i & 0x20) ? '1' : '0', @@ -293,20 +291,20 @@ cl_uc390_hw::print_info(class cl_console *con) (i & 0x04) ? '1' : '0', (i & 0x02) ? '1' : '0', (i & 0x01) ? '1' : '0'); - i = uc->get_mem (MEM_SFR, DPS); + i = sfr->get (DPS); con->dd_printf ("\tDPS 0x%02x: ID1 %c ID0 %c TSL %c SEL %c\n", - i, + i, (i & 0x80) ? '1' : '0', (i & 0x40) ? '1' : '0', (i & 0x20) ? '1' : '0', (i & 0x01) ? '1' : '0'); - l = uc->get_mem (MEM_SFR, DPX) * 256*256 + - uc->get_mem (MEM_SFR, DPH) * 256 + - uc->get_mem (MEM_SFR, DPL); + l = sfr->get (DPX) * 256*256 + + sfr->get (DPH) * 256 + + sfr->get (DPL); con->dd_printf ("\tDPTR 0x%06x\n", l); - l = uc->get_mem (MEM_SFR, DPX1) * 256*256 + - uc->get_mem (MEM_SFR, DPH1) * 256 + - uc->get_mem (MEM_SFR, DPL1); + l = sfr->get (DPX1) * 256*256 + + sfr->get (DPH1) * 256 + + sfr->get (DPL1); con->dd_printf ("\tDPTR1 0x%06x\n", l); }