X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fs51.src%2Fpca.cc;h=b9eeef394d8f6a46988f7c834bb6592604d7206f;hb=90f4aedaef8a2310573eef905f95c671f84e5cde;hp=3497fa2cddf11a8dd0068f8856e7bdb2d27b57d0;hpb=f27da39dbcab5678aca6d8462f1cc37a643f37e9;p=fw%2Fsdcc diff --git a/sim/ucsim/s51.src/pca.cc b/sim/ucsim/s51.src/pca.cc index 3497fa2c..b9eeef39 100644 --- a/sim/ucsim/s51.src/pca.cc +++ b/sim/ucsim/s51.src/pca.cc @@ -77,17 +77,17 @@ void cl_pca::added_to_uc(void) { uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false, - "PCA module #4", 5)); + "PCA module #4", 5)); uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF3, 0x0033, false, - "PCA module #3", 5)); + "PCA module #3", 5)); uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF2, 0x0033, false, - "PCA module #2", 5)); + "PCA module #2", 5)); uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF1, 0x0033, false, - "PCA module #1", 5)); + "PCA module #1", 5)); uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF0, 0x0033, false, - "PCA module #0", 5)); + "PCA module #0", 5)); uc->it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCF, 0x0033, false, - "PCA counter", 5)); + "PCA counter", 5)); } void @@ -103,7 +103,7 @@ cl_pca::write(class cl_memory_cell *cell, t_mem *val) bit_ECF = *val & bmECF; t_mem o= clk_source; if ((clk_source= *val & (bmCPS1|bmCPS0)) != o) - t0_overflows= ECI_edge= 0; + t0_overflows= ECI_edge= 0; } else if (cell == cell_ccon) { @@ -113,31 +113,31 @@ cl_pca::write(class cl_memory_cell *cell, t_mem *val) { int i; for (i= 0; i < 5; i++) - { - if (cell == cell_ccapm[i]) - { - t_mem o= ccapm[i]; - ccapm[i]= *val & 0xff; - if (o != ccapm[i]) - cex_neg[i]= cex_pos[i]= DD_FALSE; - } - else - { - if (ccapm[i] & (bmMAT|bmTOG)) - { - if (cell == cell_ccapl[i]) - { - cell_ccapm[i]->set_bit0(bmECOM); - ccapm[i]= cell_ccapm[i]->get(); - } - else if (cell == cell_ccaph[i]) - { - cell_ccapm[i]->set_bit1(bmECOM); - ccapm[i]= cell_ccapm[i]->get(); - } - } - } - } + { + if (cell == cell_ccapm[i]) + { + t_mem o= ccapm[i]; + ccapm[i]= *val & 0xff; + if (o != ccapm[i]) + cex_neg[i]= cex_pos[i]= DD_FALSE; + } + else + { + if (ccapm[i] & (bmMAT|bmTOG)) + { + if (cell == cell_ccapl[i]) + { + cell_ccapm[i]->set_bit0(bmECOM); + ccapm[i]= cell_ccapm[i]->get(); + } + else if (cell == cell_ccaph[i]) + { + cell_ccapm[i]->set_bit1(bmECOM); + ccapm[i]= cell_ccapm[i]->get(); + } + } + } + } } } @@ -149,11 +149,11 @@ cl_pca::mem_cell_changed(class cl_m *mem, t_addr addr) if (mem && sfr && mem == sfr) { if (addr == addr_ccapXl) - ccapXl= sfr->get_cell(addr_ccapXl); + ccapXl= sfr->get_cell(addr_ccapXl); else if (addr == addr_ccapXh) - ccapXh= sfr->get_cell(addr_ccapXh); + ccapXh= sfr->get_cell(addr_ccapXh); else if (addr == addr_ccapmX) - ccapmX= sfr->get_cell(addr_ccapmX); + ccapmX= sfr->get_cell(addr_ccapmX); } }*/ @@ -196,22 +196,22 @@ cl_pca::do_pca_counter(int cycles) while (cycles--) { if (cell_cl->add(1) == 0) - { - int i; - for (i= 0; i < 5; i++) - if (ccapm[i] & bmPWM) - cell_ccapl[i]->set(cell_ccaph[i]->get()); - if (cell_ch->add(1) == 0) - { - // CH,CL overflow - cell_ccon->set_bit1(bmCF); - do_pca_module(0); - do_pca_module(1); - do_pca_module(2); - do_pca_module(3); - do_pca_module(4); - } - } + { + int i; + for (i= 0; i < 5; i++) + if (ccapm[i] & bmPWM) + cell_ccapl[i]->set(cell_ccaph[i]->get()); + if (cell_ch->add(1) == 0) + { + // CH,CL overflow + cell_ccon->set_bit1(bmCF); + do_pca_module(0); + do_pca_module(1); + do_pca_module(2); + do_pca_module(3); + do_pca_module(4); + } + } } } @@ -247,33 +247,33 @@ cl_pca::do_pca_module(int nr) { // Comparator enabled if (cell_cl->get() == cell_ccapl[nr]->get() && - cell_ch->get() == cell_ccaph[nr]->get()) - { - // Match - if (nr == 4 && - (bit_WDTE)) - { - reset(); - return; - } - cell_ccon->set_bit1(bmCCF[nr]); - if (ccapm[nr] & bmTOG) - { - // Toggle - sfr->set(P1, sfr->get(P1) ^ bmCEX[nr]); - } - } + cell_ch->get() == cell_ccaph[nr]->get()) + { + // Match + if (nr == 4 && + (bit_WDTE)) + { + reset(); + return; + } + cell_ccon->set_bit1(bmCCF[nr]); + if (ccapm[nr] & bmTOG) + { + // Toggle + sfr->set(P1, sfr->get(P1) ^ bmCEX[nr]); + } + } if (ccapm[nr] & bmPWM) - { - // PWM - /*if (cell_cl->get() == 0) - cell_ccapl[nr]->set(cell_ccaph[nr]->get());*/ - if (cell_cl->get() < cell_ccapl[nr]->get()) - //sfr->set(P1, sfr->get(P1) & ~(bmCEX[nr])); - sfr->set_bit1(P1, bmCEX[nr]); - else - sfr->set_bit1(P1, bmCEX[nr]); - } + { + // PWM + /*if (cell_cl->get() == 0) + cell_ccapl[nr]->set(cell_ccaph[nr]->get());*/ + if (cell_cl->get() < cell_ccapl[nr]->get()) + //sfr->set(P1, sfr->get(P1) & ~(bmCEX[nr])); + sfr->set_bit1(P1, bmCEX[nr]); + else + sfr->set_bit1(P1, bmCEX[nr]); + } } } @@ -298,22 +298,22 @@ cl_pca::happen(class cl_hw *where, enum hw_event he, void *params) t_mem p1n= ep->new_pins & ep->new_value; t_mem p1o= ep->pins & ep->prev_value; if (!(p1n & bmECI) && - (p1o & bmECI)) - ECI_edge++; + (p1o & bmECI)) + ECI_edge++; int i; for (i= 0; i < 5; i++) - { - if (!(p1n & bmCEX[i]) && - (p1o & bmCEX[i])) - cex_neg[i]= DD_TRUE; - else if ((p1n & bmCEX[i]) && - !(p1o & bmCEX[i])) - cex_pos[i]= DD_TRUE; - } + { + if (!(p1n & bmCEX[i]) && + (p1o & bmCEX[i])) + cex_neg[i]= DD_TRUE; + else if ((p1n & bmCEX[i]) && + !(p1o & bmCEX[i])) + cex_pos[i]= DD_TRUE; + } } else if (where->cathegory == HW_TIMER && - he == EV_OVERFLOW && - where->id == 0) + he == EV_OVERFLOW && + where->id == 0) { t0_overflows++; } @@ -321,7 +321,7 @@ cl_pca::happen(class cl_hw *where, enum hw_event he, void *params) void -cl_pca::print_info(class cl_console *con) +cl_pca::print_info(class cl_console_base *con) { con->dd_printf("%s[%d] FIXME\n", id_string, id); }