X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=sim%2Fucsim%2Fs51.src%2Finterrupt.cc;h=f8a8f8d31f56907962d50c2beceb02e1877fac64;hb=90f4aedaef8a2310573eef905f95c671f84e5cde;hp=6cded08259572a98a51dcb7cd07d45ea7cee71be;hpb=109dd226aad40f4f2f122e6ccfc7f038610a5ceb;p=fw%2Fsdcc diff --git a/sim/ucsim/s51.src/interrupt.cc b/sim/ucsim/s51.src/interrupt.cc index 6cded082..f8a8f8d3 100644 --- a/sim/ucsim/s51.src/interrupt.cc +++ b/sim/ucsim/s51.src/interrupt.cc @@ -25,32 +25,116 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /*@1@*/ +// prj +#include "utils.h" + // sim #include "itsrccl.h" // local #include "interruptcl.h" #include "regs51.h" +//#include "uc51cl.h" +#include "types51.h" cl_interrupt::cl_interrupt(class cl_uc *auc): cl_hw(auc, HW_INTERRUPT, 0, "irq") -{} +{ + was_reti= DD_FALSE; +} -/*int +int cl_interrupt::init(void) { + sfr= uc->address_space(MEM_SFR_ID); + if (sfr) + { + //sfr->register_hw(IE, this, 0); + register_cell(sfr, IE, 0, wtd_restore); + register_cell(sfr, TCON, &cell_tcon, wtd_restore_write); + bit_INT0= sfr->read(P3) & bm_INT0; + bit_INT1= sfr->read(P3) & bm_INT1; + } return(0); +} + +void +cl_interrupt::added_to_uc(void) +{ + uc->it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true, + "external #0", 1)); + uc->it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true, + "external #1", 3)); +} + +void +cl_interrupt::write(class cl_memory_cell *cell, t_mem *val) +{ + if (cell == cell_tcon) + { + bit_IT0= *val & bmIT0; + bit_IT1= *val & bmIT1; + } + else + // IE register + was_reti= DD_TRUE; +} + +/*void +cl_interrupt::mem_cell_changed(class cl_m *mem, t_addr addr) +{ }*/ +int +cl_interrupt::tick(int cycles) +{ + if (!bit_IT0 && !bit_INT0) + cell_tcon->set_bit1(bmIE0); + if (!bit_IT1 && !bit_INT1) + cell_tcon->set_bit1(bmIE1); + return(resGO); +} + +void +cl_interrupt::reset(void) +{ + was_reti= DD_FALSE; +} + +void +cl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params) +{ + struct ev_port_changed *ep= (struct ev_port_changed *)params; + + if (where->cathegory == HW_PORT && + he == EV_PORT_CHANGED && + ep->id == 3) + { + t_mem p3n= ep->new_pins & ep->new_value; + t_mem p3o= ep->pins & ep->prev_value; + if (bit_IT0 && + !(p3n & bm_INT0) && + (p3o & bm_INT0)) + cell_tcon->set_bit1(bmIE0); + if (bit_IT1 && + !(p3n & bm_INT1) && + (p3o & bm_INT1)) + cell_tcon->set_bit1(bmIE1); + bit_INT0= p3n & bm_INT0; + bit_INT1= p3n & bm_INT1; + } +} + + void -cl_interrupt::print_info(class cl_console *con) +cl_interrupt::print_info(class cl_console_base *con) { - int ie= uc->get_mem(MEM_SFR, IE); + int ie= sfr->get(IE); int i; con->dd_printf("Interrupts are %s. Interrupt sources:\n", - (ie&bmEA)?"enabled":"disabled"); + (ie&bmEA)?"enabled":"disabled"); con->dd_printf(" Handler En Pr Req Act Name\n"); for (i= 0; i < uc->it_sources->count; i++) { @@ -59,10 +143,10 @@ cl_interrupt::print_info(class cl_console *con) con->dd_printf(" %-3s", (ie&(is->ie_mask))?"en":"dis"); con->dd_printf(" %2d", uc->it_priority(is->ie_mask)); con->dd_printf(" %-3s", - (uc->get_mem(MEM_SFR, is->src_reg)&(is->src_mask))? - "YES":"no"); + (sfr->get(is->src_reg)&(is->src_mask))? + "YES":"no"); con->dd_printf(" %-3s", (is->active)?"act":"no"); - con->dd_printf(" %s", is->name); + con->dd_printf(" %s", object_name(is)); con->dd_printf("\n"); } con->dd_printf("Active interrupt service(s):\n"); @@ -71,13 +155,14 @@ cl_interrupt::print_info(class cl_console *con) { class it_level *il= (class it_level *)(uc->it_levels->at(i)); if (il->level >= 0) - { - con->dd_printf(" %2d", il->level); - con->dd_printf(" 0x%06x", il->addr); - con->dd_printf(" 0x%06x", il->PC); - con->dd_printf(" %s", (il->source)?(il->source->name):"nothing"); - con->dd_printf("\n"); - } + { + con->dd_printf(" %2d", il->level); + con->dd_printf(" 0x%06x", il->addr); + con->dd_printf(" 0x%06x", il->PC); + con->dd_printf(" %s", (il->source)?(object_name(il->source)): + "nothing"); + con->dd_printf("\n"); + } } }