X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gr-sounder%2Fsrc%2Ffpga%2Ftop%2Fusrp_sounder.qsf;h=4d60f5f13f78964a43f75c175965c19a4226f2e1;hb=592153b2b94ae12e85598fa4a32feb5849bb6163;hp=5ff52583f362aac0f0d269cec55e781fd39292e6;hpb=2711e51f33e4c83b07d8293ceca5d6db7830656e;p=debian%2Fgnuradio

diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qsf b/gr-sounder/src/fpga/top/usrp_sounder.qsf
old mode 100755
new mode 100644
index 5ff52583..4d60f5f1
--- a/gr-sounder/src/fpga/top/usrp_sounder.qsf
+++ b/gr-sounder/src/fpga/top/usrp_sounder.qsf
@@ -236,7 +236,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
 set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name INC_PLC_MODE OFF
 set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
 set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
@@ -368,13 +368,15 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 
-set_global_assignment -name VERILOG_FILE ../lib/strobe.v
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC
 set_global_assignment -name VERILOG_FILE ../lib/lfsr_constants.v
 set_global_assignment -name VERILOG_FILE ../lib/lfsr.v
 set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
 set_global_assignment -name VERILOG_FILE ../lib/dacpll.v
 set_global_assignment -name VERILOG_FILE ../lib/sounder_rx.v
 set_global_assignment -name VERILOG_FILE ../lib/sounder_tx.v
+set_global_assignment -name VERILOG_FILE ../lib/sounder_ctrl.v
 set_global_assignment -name VERILOG_FILE ../lib/sounder.v
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v
@@ -390,4 +392,5 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_co
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sounder.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE usrp_sounder.v
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file