X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gdbserver%2Fgdb-server.c;h=eca6597b470d0fae819500d6f1fface020afde30;hb=refs%2Fheads%2Fdebian;hp=71ab440163f352b7f9bdb4888f58ede9eabefc68;hpb=3b443dc1c8690ee4b45f477cd83165dca700e60a;p=fw%2Fstlink diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 71ab440..eca6597 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1,4 +1,3 @@ -#define DEBUG 0 /* * Copyright (C) 2011 Peter Zotov * Use of this source code is governed by a BSD-style @@ -10,7 +9,6 @@ #include #include #include -#include #include #include #ifdef __MINGW32__ @@ -22,14 +20,10 @@ #endif #include +#include #include "gdb-remote.h" - -#define DEFAULT_LOGGING_LEVEL 50 -#define DEFAULT_GDB_LISTEN_PORT 4242 - -#define STRINGIFY_inner(name) #name -#define STRINGIFY(name) STRINGIFY_inner(name) +#include "gdb-server.h" #define FLASH_BASE 0x08000000 @@ -54,6 +48,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +static void init_cache (stlink_t *sl); static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { @@ -178,11 +173,11 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level, 0); + sl = stlink_open_usb(state.logging_level, state.reset, NULL); if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(state.logging_level, 0); + sl = stlink_v1_open(state.logging_level, state.reset); if(sl == NULL) return 1; break; } @@ -190,16 +185,17 @@ int main(int argc, char** argv) { connected_stlink = sl; signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); if (state.reset) { stlink_reset(sl); } - printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); voltage = stlink_target_voltage(sl); if (voltage != -1) { - printf("Target voltage is %d mV.\n", voltage); + ILOG("Target voltage is %d mV.\n", voltage); } sl->verbose=0; @@ -213,8 +209,12 @@ int main(int argc, char** argv) { } #endif + init_cache(sl); + do { - serve(sl, &state); + if (serve(sl, &state)) { + sleep (1); // don't go bezurk if serve returns with error + } /* Continue */ stlink_run(sl); @@ -311,15 +311,84 @@ static const char* const memory_map_template_F4 = " " //Sector 4 " 0x10000" //64kB " " - " " //Sectors 5..11 + " " //Sectors 5..11 " 0x20000" //128kB " " " " // peripheral regs + " " // AHB3 Peripherals " " // cortex regs " " // bootrom " " // option byte area ""; +static const char* const memory_map_template_F4_HD = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " // fmc bank 1 (nor/psram/sram) + " " // fmc bank 2 & 3 (nand flash) + " " // fmc bank 4 (pc card) + " " // fmc sdram bank 1 & 2 + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..11 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F2 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5.. + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 KB) + " " // SRAM1 (96 KB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + static const char* const memory_map_template = "" "" // option byte area ""; +static const char* const memory_map_template_F7 = + "" + "" + "" + " " // ITCM ram 16kB + " " // ITCM flash + " " // sram + " " // Sectors 0..3 + " 0x8000" // 32kB + " " + " " // Sector 4 + " 0x20000" // 128kB + " " + " " // Sectors 5..7 + " 0x40000" // 128kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) { strcpy(map, memory_map_template_F4); + } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) { + strcpy(map, memory_map_template_F7); + } else if(sl->chip_id==STM32_CHIPID_F4_HD) { + strcpy(map, memory_map_template_F4_HD); + } else if(sl->chip_id==STM32_CHIPID_F2) { + snprintf(map, 4096, memory_map_template_F2, + sl->flash_size, + sl->sram_size, + sl->flash_size - 0x20000, + sl->sys_base, sl->sys_size); + } else if(sl->chip_id==STM32_CHIPID_L4) { + snprintf(map, 4096, memory_map_template_L4, + sl->flash_size, sl->flash_size); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, @@ -382,13 +488,13 @@ struct code_hw_watchpoint { struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { -#if DEBUG - printf("init watchpoints\n"); -#endif + uint32_t data; + DLOG("init watchpoints\n"); + stlink_read_debug32(sl, 0xE000EDFC, &data); + data |= 1<<24; // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, - stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); + stlink_write_debug32(sl, 0xE000EDFC, data); // make sure all watchpoints are cleared for(int i = 0; i < DATA_WATCH_NUM; i++) { @@ -397,10 +503,10 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) -{ +static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, + stm32_addr_t addr, unsigned int len) { int i = 0; - uint32_t mask; + uint32_t mask, dummy; // computer mask // find a free watchpoint @@ -417,9 +523,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr for(i = 0; i < DATA_WATCH_NUM; i++) { // is this an empty slot ? if(data_watches[i].fun == WATCHDISABLED) { -#if DEBUG - printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); -#endif + DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); data_watches[i].fun = wf; data_watches[i].addr = addr; @@ -435,15 +539,13 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16); + stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); return 0; } } } -#if DEBUG - printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); -#endif + DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); return -1; } @@ -453,9 +555,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) for(i = 0 ; i < DATA_WATCH_NUM; i++) { if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { -#if DEBUG - printf("delete watchpoint %d addr %x\n", i, addr); -#endif + DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); @@ -464,15 +564,14 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) } } -#if DEBUG - printf("failure: delete watchpoint addr %x\n", addr); -#endif + DLOG("failure: delete watchpoint addr %x\n", addr); return -1; } -#define CODE_BREAK_NUM 6 -#define CODE_LIT_NUM 2 +int code_break_num; +int code_lit_num; +#define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -481,37 +580,42 @@ struct code_hw_breakpoint { int type; }; -struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; +struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { + unsigned int val; memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); - if (((val & 3) != 1) || - ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || - (((val >> 8) & 0xf) != CODE_LIT_NUM)){ - fprintf(stderr, "[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, - ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); - } + stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val); + code_break_num = ((val >> 4) & 0xf); + code_lit_num = ((val >> 8) & 0xf); + ILOG("Found %i hw breakpoint registers\n", code_break_num); - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); } } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr = addr & ~0x3; - int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + stm32_addr_t fpb_addr; + uint32_t mask; + int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; if(addr & 1) { - fprintf(stderr, "update_code_breakpoint: unaligned address %08x\n", addr); + ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return -1; } + if (sl->chip_id==STM32_CHIPID_F7) { + fpb_addr = addr; + } else { + fpb_addr = addr & ~0x3; + } + int id = -1; - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { if(fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; @@ -528,24 +632,27 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { brk->addr = fpb_addr; - if(set) brk->type |= type; - else brk->type &= ~type; + if (sl->chip_id==STM32_CHIPID_F7) { + if(set) brk->type = type; + else brk->type = 0; + + mask = (brk->addr) | 1; + } else { + if(set) brk->type |= type; + else brk->type &= ~type; + + mask = (brk->addr) | 1 | (brk->type << 30); + } if(brk->type == 0) { -#if DEBUG - printf("clearing hw break %d\n", id); -#endif + DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - uint32_t mask = (brk->addr) | 1 | (brk->type << 30); - -#if DEBUG - printf("setting hw break %d at %08x (%d)\n", - id, brk->addr, brk->type); - printf("reg %08x \n", - mask); -#endif + DLOG("setting hw break %d at %08x (%d)\n", + id, brk->addr, brk->type); + DLOG("reg %08x \n", + mask); stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } @@ -567,13 +674,13 @@ static struct flash_block* flash_root; static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { - fprintf(stderr, "flash_add_block: incorrect bounds\n"); + ELOG("flash_add_block: incorrect bounds\n"); return -1; } stlink_calculate_pagesize(sl, addr); if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { - fprintf(stderr, "flash_add_block: unaligned block\n"); + ELOG("flash_add_block: unaligned block\n"); return -1; } @@ -616,14 +723,14 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { } if(fit_blocks == 0) { - fprintf(stderr, "Unfit data block %08x -> %04x\n", addr, length); + ELOG("Unfit data block %08x -> %04x\n", addr, length); return -1; } if(fit_length != length) { - fprintf(stderr, "warning: data block %08x -> %04x truncated to %04x\n", + WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length); - fprintf(stderr, "(this is not an error, just a GDB glitch)\n"); + WLOG("(this is not an error, just a GDB glitch)\n"); } return 0; @@ -634,25 +741,24 @@ static int flash_go(stlink_t *sl) { // Some kinds of clock settings do not allow writing to flash. stlink_reset(sl); + stlink_force_debug(sl); for(struct flash_block* fb = flash_root; fb; fb = fb->next) { -#if DEBUG - printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length); -#endif + DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + unsigned length = fb->length - (page - fb->addr); //Update FLASH_PAGE stlink_calculate_pagesize(sl, page); -#if DEBUG - printf("flash_do: page %08x\n", page); -#endif - + DLOG("flash_do: page %08x\n", page); + unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - length > FLASH_PAGE ? FLASH_PAGE : length) < 0) + send, 0) < 0) goto error; + length -= send; + } } @@ -672,6 +778,162 @@ error: return error; } +#define CLIDR 0xE000ED78 +#define CTR 0xE000ED7C +#define CCSIDR 0xE000ED80 +#define CSSELR 0xE000ED84 +#define CCR 0xE000ED14 +#define CCR_DC (1 << 16) +#define CCR_IC (1 << 17) +#define DCCSW 0xE000EF6C +#define ICIALLU 0xE000EF50 + +struct cache_level_desc +{ + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; +}; + +struct cache_desc_t +{ + /* Minimal line size in bytes. */ + unsigned int dminline; + unsigned int iminline; + + /* Last level of unification (uniprocessor). */ + unsigned int louu; + + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; +}; + +static struct cache_desc_t cache_desc; + +/* Return the smallest R so that V <= (1 << R). Not performance critical. */ +static unsigned ceil_log2(unsigned v) +{ + unsigned res; + for (res = 0; (1U << res) < v; res++) + ; + return res; +} + +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) +{ + unsigned int ccsidr; + unsigned int log2_nsets; + + stlink_read_debug32(sl, CCSIDR, &ccsidr); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +} + +static void init_cache (stlink_t *sl) { + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + /* Assume only F7 has a cache. */ + if(sl->chip_id!=STM32_CHIPID_F7) + return; + + stlink_read_debug32(sl, CLIDR, &clidr); + stlink_read_debug32(sl, CCR, &ccr); + stlink_read_debug32(sl, CTR, &ctr); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for(i = 0; i < 7; i++) + { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if(ct == 2 || ct == 3 || ct == 4) + { + /* Data. */ + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if(ct == 1 || ct == 3) + { + /* Instruction. */ + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } + } +} + +static void cache_flush(stlink_t *sl, unsigned ccr) { + int level; + + if (ccr & CCR_DC) + for (level = cache_desc.louu - 1; level >= 0; level--) + { + struct cache_level_desc *desc = &cache_desc.dcache[level]; + unsigned addr; + unsigned max_addr = 1 << desc->width; + unsigned way_sh = 32 - desc->log2_nways; + + /* D-cache clean by set-ways. */ + for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) + { + unsigned int way; + + for (way = 0; way < desc->nways; way++) + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } + } + + /* Invalidate all I-cache to oPU. */ + if (ccr & CCR_IC) + stlink_write_debug32(sl, ICIALLU, 0); +} + +static int cache_modified; + +static void cache_change(stm32_addr_t start, unsigned count) +{ + if (count == 0) + return; + (void)start; + cache_modified = 1; +} + +static void cache_sync(stlink_t *sl) +{ + unsigned ccr; + + if(sl->chip_id!=STM32_CHIPID_F7) + return; + if (!cache_modified) + return; + cache_modified = 0; + + stlink_read_debug32(sl, CCR, &ccr); + if (ccr & (CCR_IC | CCR_DC)) + cache_flush(sl, ccr); +} + int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { @@ -698,7 +960,7 @@ int serve(stlink_t *sl, st_state_t *st) { return 1; } - printf("Listening at *:%d...\n", st->listen_port); + ILOG("Listening at *:%d...\n", st->listen_port); int client = accept(sock, NULL, NULL); //signal (SIGINT, SIG_DFL); @@ -716,7 +978,7 @@ int serve(stlink_t *sl, st_state_t *st) { init_code_breakpoints(sl); init_data_watchpoints(sl); - printf("GDB connected.\n"); + ILOG("GDB connected.\n"); /* * To allow resetting the chip from GDB it is required to @@ -729,13 +991,14 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_recv_packet(client, &packet); if(status < 0) { - fprintf(stderr, "cannot recv: %d\n", status); + ELOG("cannot recv: %d\n", status); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } -#if DEBUG - printf("recv: %s\n", packet); -#endif + DLOG("recv: %s\n", packet); char* reply = NULL; reg regp; @@ -758,12 +1021,12 @@ int serve(stlink_t *sl, st_state_t *st) { char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); -#if DEBUG - printf("query: %s;%s\n", queryName, params); -#endif + DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 + || sl->chip_id==STM32_CHIPID_F4_HD + || sl->chip_id==STM32_CHIPID_F7) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { @@ -783,10 +1046,8 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); -#if DEBUG - printf("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", - type, op, annex, addr, length); -#endif + DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", + type, op, annex, addr, length); const char* data = NULL; @@ -820,9 +1081,8 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume -#if DEBUG - printf("Rcmd: resume\n"); -#endif + DLOG("Rcmd: resume\n"); + cache_sync(sl); stlink_run(sl); reply = strdup("OK"); @@ -831,19 +1091,15 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); -#if DEBUG - printf("Rcmd: halt\n"); -#endif + DLOG("Rcmd: halt\n"); } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset reply = strdup("OK"); - stlink_jtag_reset(sl, 1); stlink_jtag_reset(sl, 0); + stlink_jtag_reset(sl, 1); stlink_force_debug(sl); -#if DEBUG - printf("Rcmd: jtag_reset\n"); -#endif + DLOG("Rcmd: jtag_reset\n"); } else if (!strncmp(params,"7265736574",10)) { //reset reply = strdup("OK"); @@ -852,14 +1108,9 @@ int serve(stlink_t *sl, st_state_t *st) { init_code_breakpoints(sl); init_data_watchpoints(sl); -#if DEBUG - printf("Rcmd: reset\n"); -#endif + DLOG("Rcmd: reset\n"); } else { -#if DEBUG - printf("Rcmd: %s\n", params); -#endif - + DLOG("Rcmd: %s\n", params); } } @@ -888,10 +1139,8 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); -#if DEBUG - printf("FlashErase: addr:%08x,len:%04x\n", - addr, length); -#endif + DLOG("FlashErase: addr:%08x,len:%04x\n", + addr, length); if(flash_add_block(addr, length, sl) < 0) { reply = strdup("E00"); @@ -926,9 +1175,7 @@ int serve(stlink_t *sl, st_state_t *st) { if(dec_index % 2 != 0) dec_index++; -#if DEBUG - printf("binary packet %d -> %d\n", data_length, dec_index); -#endif + DLOG("binary packet %d -> %d\n", data_length, dec_index); if(flash_populate(addr, decoded, dec_index) < 0) { reply = strdup("E00"); @@ -954,12 +1201,16 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'c': + cache_sync(sl); stlink_run(sl); while(1) { int status = gdb_check_for_interrupt(client); if(status < 0) { - fprintf(stderr, "cannot check for int: %d\n", status); + ELOG("cannot check for int: %d\n", status); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } @@ -980,6 +1231,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': + cache_sync(sl); stlink_step(sl); reply = strdup("S05"); // TRAP @@ -1105,6 +1357,12 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + if (count_rnd > sl->flash_pgsz) + count_rnd = sl->flash_pgsz; + if (count_rnd > 0x1800) + count_rnd = 0x1800; + if (count_rnd < count) + count = count_rnd; stlink_read_mem32(sl, start - adj_start, count_rnd); @@ -1134,6 +1392,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); start += align_count; count -= align_count; hexdata += 2*align_count; @@ -1148,6 +1407,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); count -= aligned_count; start += aligned_count; hexdata += 2*aligned_count; @@ -1160,6 +1420,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, count); + cache_change(start, count); } reply = strdup("OK"); break; @@ -1267,15 +1528,16 @@ int serve(stlink_t *sl, st_state_t *st) { } if(reply) { -#if DEBUG - printf("send: %s\n", reply); -#endif + DLOG("send: %s\n", reply); int result = gdb_send_packet(client, reply); if(result != 0) { - fprintf(stderr, "cannot send: %d\n", result); + ELOG("cannot send: %d\n", result); free(reply); free(packet); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } @@ -1285,5 +1547,9 @@ int serve(stlink_t *sl, st_state_t *st) { free(packet); } +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif + return 0; }