X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gdbserver%2Fgdb-server.c;h=eca6597b470d0fae819500d6f1fface020afde30;hb=refs%2Fheads%2Fdebian;hp=49c7e6dd4ca1f11cfb8b68a46eeb0d9f0b506676;hpb=54c8d2ca8b99c27761b45f35cd17f79512cb4a23;p=fw%2Fstlink

diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c
index 49c7e6d..eca6597 100644
--- a/gdbserver/gdb-server.c
+++ b/gdbserver/gdb-server.c
@@ -9,7 +9,6 @@
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
-#include <signal.h>
 #include <unistd.h>
 #include <sys/types.h>
 #ifdef __MINGW32__
@@ -174,11 +173,11 @@ int main(int argc, char** argv) {
     parse_options(argc, argv, &state);
     switch (state.stlink_version) {
         case 2:
-	        sl = stlink_open_usb(state.logging_level, 0, NULL);
+            sl = stlink_open_usb(state.logging_level, state.reset, NULL);
             if(sl == NULL) return 1;
             break;
         case 1:
-            sl = stlink_v1_open(state.logging_level, 0);
+            sl = stlink_v1_open(state.logging_level, state.reset);
             if(sl == NULL) return 1;
             break;
     }
@@ -186,6 +185,7 @@ int main(int argc, char** argv) {
     connected_stlink = sl;
     signal(SIGINT, &cleanup);
     signal(SIGTERM, &cleanup);
+    signal(SIGSEGV, &cleanup);
 
     if (state.reset) {
         stlink_reset(sl);
@@ -370,6 +370,25 @@ static const char* const memory_map_template_F2 =
     "  <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>"         // option byte area
     "</memory-map>";
 
+static const char* const memory_map_template_L4 =
+    "<?xml version=\"1.0\"?>"
+    "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
+    "     \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
+    "<memory-map>"
+    "  <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>"        // code = sram, bootrom or flash; flash is bigger
+    "  <memory type=\"ram\" start=\"0x10000000\" length=\"0x8000\"/>"       // SRAM2 (32 KB)
+    "  <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>"      // SRAM1 (96 KB)
+    "  <memory type=\"flash\" start=\"0x08000000\" length=\"0x%zx\">"
+    "    <property name=\"blocksize\">0x800</property>"
+    "  </memory>"
+    "  <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>"   // peripheral regs
+    "  <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>"   // AHB3 Peripherals
+    "  <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>"   // cortex regs
+    "  <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>"       // bootrom
+    "  <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>"         // option byte area
+    "  <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>"         // option byte area
+    "</memory-map>";
+
 static const char* const memory_map_template =
     "<?xml version=\"1.0\"?>"
     "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
@@ -427,6 +446,9 @@ char* make_memory_map(stlink_t *sl) {
                 sl->sram_size,
                 sl->flash_size - 0x20000,
                 sl->sys_base, sl->sys_size);
+    } else if(sl->chip_id==STM32_CHIPID_L4) {
+        snprintf(map, 4096, memory_map_template_L4,
+                sl->flash_size, sl->flash_size);
     } else {
         snprintf(map, 4096, memory_map_template,
                 sl->flash_size,
@@ -466,11 +488,13 @@ struct code_hw_watchpoint {
 struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
 
 static void init_data_watchpoints(stlink_t *sl) {
+    uint32_t data;
     DLOG("init watchpoints\n");
 
+    stlink_read_debug32(sl, 0xE000EDFC, &data);
+    data |= 1<<24;
     // set trcena in debug command to turn on dwt unit
-    stlink_write_debug32(sl, 0xE000EDFC,
-            stlink_read_debug32(sl, 0xE000EDFC) | (1<<24));
+    stlink_write_debug32(sl, 0xE000EDFC, data);
 
     // make sure all watchpoints are cleared
     for(int i = 0; i < DATA_WATCH_NUM; i++) {
@@ -482,7 +506,7 @@ static void init_data_watchpoints(stlink_t *sl) {
 static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
                                stm32_addr_t addr, unsigned int len) {
     int i = 0;
-    uint32_t mask;
+    uint32_t mask, dummy;
 
     // computer mask
     // find a free watchpoint
@@ -515,7 +539,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
                 stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
 
                 // just to make sure the matched bit is clear !
-                stlink_read_debug32(sl,  0xE0001028 + i * 16);
+                stlink_read_debug32(sl,  0xE0001028 + i * 16, &dummy);
                 return 0;
             }
         }
@@ -559,9 +583,10 @@ struct code_hw_breakpoint {
 struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
 
 static void init_code_breakpoints(stlink_t *sl) {
+    unsigned int val;
     memset(sl->q_buf, 0, 4);
     stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
-    unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
+    stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val);
     code_break_num = ((val >> 4) & 0xf);
     code_lit_num = ((val >> 8) & 0xf);
 
@@ -730,7 +755,7 @@ static int flash_go(stlink_t *sl) {
             DLOG("flash_do: page %08x\n", page);
             unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length;
             if(stlink_write_flash(sl, page, fb->data + (page - fb->addr),
-                        send) < 0)
+                        send, 0) < 0)
                 goto error;
             length -= send;
             
@@ -790,7 +815,7 @@ static struct cache_desc_t cache_desc;
 static unsigned ceil_log2(unsigned v)
 {
   unsigned res;
-  for (res = 0; (1 << res) < v; res++)
+  for (res = 0; (1U << res) < v; res++)
     ;
   return res;
 }
@@ -799,7 +824,8 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc)
 {
   unsigned int ccsidr;
   unsigned int log2_nsets;
-  ccsidr = stlink_read_debug32(sl, CCSIDR);
+
+  stlink_read_debug32(sl, CCSIDR, &ccsidr);
   desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
   desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
   desc->log2_nways = ceil_log2 (desc->nways);
@@ -819,9 +845,9 @@ static void init_cache (stlink_t *sl) {
   if(sl->chip_id!=STM32_CHIPID_F7)
     return;
 
-  clidr = stlink_read_debug32(sl, CLIDR);
-  ccr = stlink_read_debug32(sl, CCR);
-  ctr = stlink_read_debug32(sl, CTR);
+  stlink_read_debug32(sl, CLIDR, &clidr);
+  stlink_read_debug32(sl, CCR, &ccr);
+  stlink_read_debug32(sl, CTR, &ctr);
   cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
   cache_desc.iminline = 4 << (ctr & 0x0f);
   cache_desc.louu = (clidr >> 27) & 7;
@@ -903,7 +929,7 @@ static void cache_sync(stlink_t *sl)
     return;
   cache_modified = 0;
 
-  ccr = stlink_read_debug32(sl, CCR);
+  stlink_read_debug32(sl, CCR, &ccr);
   if (ccr & (CCR_IC | CCR_DC))
     cache_flush(sl, ccr);
 }
@@ -1331,6 +1357,12 @@ int serve(stlink_t *sl, st_state_t *st) {
 
                 unsigned adj_start = start % 4;
                 unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4;
+                if (count_rnd > sl->flash_pgsz)
+                    count_rnd = sl->flash_pgsz;
+                if (count_rnd > 0x1800)
+                    count_rnd = 0x1800;
+                if (count_rnd < count)
+                    count = count_rnd;
 
                 stlink_read_mem32(sl, start - adj_start, count_rnd);