X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gdbserver%2Fgdb-server.c;h=851c758a9a9dcf0f6feca36645aea584c058972d;hb=9c41193a169c1078fff70fb356c53c22224e5bb9;hp=e7676219ce8151d84d80498ccd0a75cf7275fb08;hpb=d019d3fc4f34297a78bf8c38c5a06053b2707862;p=fw%2Fstlink diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index e767621..851c758 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1,5 +1,5 @@ /* -*- tab-width:8 -*- */ - +#define DEBUG 0 /* Copyright (C) 2011 Peter Zotov Use of this source code is governed by a BSD-style @@ -28,23 +28,14 @@ #define STRINGIFY(name) STRINGIFY_inner(name) #define FLASH_BASE 0x08000000 + +//Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) -#define FLASH_PAGE_MASK (~((1 << 10) - 1)) -#define FLASH_SIZE (FLASH_PAGE * 128) static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; -/* - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - */ - -#define CORE_M3_R1 0x1BA00477 -#define CORE_M3_R2 0x4BA00477 -#define CORE_M4_R0 0x2BA01477 - typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -169,16 +160,9 @@ int main(int argc, char** argv) { break; } - uint32_t chip_id = sl->chip_id; - uint32_t core_id = sl->core_id; - - /* Fix chip_id for F4 */ - if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { - printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); - chip_id = 0x413; - } + printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); - printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); + sl->verbose=0; current_memory_map = make_memory_map(sl); @@ -192,6 +176,28 @@ int main(int argc, char** argv) { return 0; } +static const char* const memory_map_template_F4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..11 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + static const char* const memory_map_template = "" "chip_id==STM32F4_CHIP_ID) { + strcpy(map, memory_map_template_F4); + } else { + snprintf(map, 4096, memory_map_template, sl->flash_size, sl->sram_size, sl->flash_size, sl->flash_pgsz, sl->sys_base, sl->sys_size); - + } return map; } @@ -256,15 +265,13 @@ static void init_data_watchpoints(stlink_t *sl) { #endif // set trcena in debug command to turn on dwt unit - stlink_read_mem32(sl, 0xE000EDFC, 4); - sl->q_buf[3] |= 1; - stlink_write_mem32(sl, 0xE000EDFC, 4); + stlink_write_debug32(sl, 0xE000EDFC, + stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); // make sure all watchpoints are cleared - memset(sl->q_buf, 0, 4); for(int i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; - stlink_write_mem32(sl, 0xe0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); } } @@ -297,25 +304,16 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr data_watches[i].mask = mask; // insert comparator address - sl->q_buf[0] = (addr & 0xff); - sl->q_buf[1] = ((addr >> 8) & 0xff); - sl->q_buf[2] = ((addr >> 16) & 0xff); - sl->q_buf[3] = ((addr >> 24) & 0xff); - - stlink_write_mem32(sl, 0xE0001020 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); // insert mask - memset(sl->q_buf, 0, 4); - sl->q_buf[0] = mask; - stlink_write_mem32(sl, 0xE0001024 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); // insert function - memset(sl->q_buf, 0, 4); - sl->q_buf[0] = wf; - stlink_write_mem32(sl, 0xE0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); // just to make sure the matched bit is clear ! - stlink_read_mem32(sl, 0xE0001028 + i * 16, 4); + stlink_read_debug32(sl, 0xE0001028 + i * 16); return 0; } } @@ -337,9 +335,8 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) printf("delete watchpoint %d addr %x\n", i, addr); #endif - memset(sl->q_buf, 0, 4); data_watches[i].fun = WATCHDISABLED; - stlink_write_mem32(sl, 0xe0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); return 0; } @@ -365,15 +362,13 @@ struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; static void init_code_breakpoints(stlink_t *sl) { memset(sl->q_buf, 0, 4); - sl->q_buf[0] = 0x03; // KEY | ENABLE - stlink_write_mem32(sl, CM3_REG_FP_CTRL, 4); + stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); printf("KARL - should read back as 0x03, not 60 02 00 00\n"); - stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); + stlink_read_debug32(sl, CM3_REG_FP_CTRL); - memset(sl->q_buf, 0, 4); for(int i = 0; i < CODE_BREAK_NUM; i++) { code_breaks[i].type = 0; - stlink_write_mem32(sl, CM3_REG_FP_COMP0 + i * 4, 4); + stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); } } @@ -407,28 +402,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { if(set) brk->type |= type; else brk->type &= ~type; - memset(sl->q_buf, 0, 4); - if(brk->type == 0) { #ifdef DEBUG printf("clearing hw break %d\n", id); #endif - stlink_write_mem32(sl, 0xe0002008 + id * 4, 4); + stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - sl->q_buf[0] = ( brk->addr & 0xff) | 1; - sl->q_buf[1] = ((brk->addr >> 8) & 0xff); - sl->q_buf[2] = ((brk->addr >> 16) & 0xff); - sl->q_buf[3] = ((brk->addr >> 24) & 0xff) | (brk->type << 6); + uint32_t mask = (brk->addr) | 1 | (brk->type << 30); #ifdef DEBUG printf("setting hw break %d at %08x (%d)\n", id, brk->addr, brk->type); - printf("reg %02x %02x %02x %02x\n", - sl->q_buf[3], sl->q_buf[2], sl->q_buf[1], sl->q_buf[0]); + printf("reg %08x \n", + mask); #endif - stlink_write_mem32(sl, 0xe0002008 + id * 4, 4); + stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } return 0; @@ -445,13 +435,14 @@ struct flash_block { static struct flash_block* flash_root; -static int flash_add_block(stm32_addr_t addr, unsigned length, - stlink_t *sl) { - if(addr < FLASH_BASE || addr + length > FLASH_BASE + FLASH_SIZE) { +static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { + + if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { fprintf(stderr, "flash_add_block: incorrect bounds\n"); return -1; } + stlink_calculate_pagesize(sl, addr); if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { fprintf(stderr, "flash_add_block: unaligned block\n"); return -1; @@ -522,17 +513,18 @@ static int flash_go(stlink_t *sl) { unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + + //Update FLASH_PAGE + stlink_calculate_pagesize(sl, page); + #ifdef DEBUG printf("flash_do: page %08x\n", page); #endif - stlink_erase_flash_page(sl, page); - if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), length > FLASH_PAGE ? FLASH_PAGE : length) < 0) goto error; - } - + } } stlink_reset(sl);