X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gdbserver%2Fgdb-server.c;h=12c7c9f94e5b59d4ee8dd6825b25d93790c30e17;hb=2c7ee49b5fe9f8c8957eb4c4b9e3aa4f9921cf12;hp=393474dd3396b2971f2588fc1b6e922d107a4e1a;hpb=af4a00a193609cf88b7d144b840d022484351568;p=fw%2Fstlink diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 393474d..12c7c9f 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -49,6 +49,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +static void init_cache (stlink_t *sl); static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { @@ -173,7 +174,7 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level, 0); + sl = stlink_open_usb(state.logging_level, 0, NULL); if(sl == NULL) return 1; break; case 1: @@ -208,6 +209,8 @@ int main(int argc, char** argv) { } #endif + init_cache(sl); + do { if (serve(sl, &state)) { sleep (1); // don't go bezurk if serve returns with error @@ -367,6 +370,25 @@ static const char* const memory_map_template_F2 = " " // option byte area ""; +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 KB) + " " // SRAM1 (96 KB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + static const char* const memory_map_template = "" "" // option byte area ""; +static const char* const memory_map_template_F7 = + "" + "" + "" + " " // ITCM ram 16kB + " " // ITCM flash + " " // sram + " " // Sectors 0..3 + " 0x8000" // 32kB + " " + " " // Sector 4 + " 0x20000" // 128kB + " " + " " // Sectors 5..7 + " 0x40000" // 128kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) { strcpy(map, memory_map_template_F4); + } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) { + strcpy(map, memory_map_template_F7); } else if(sl->chip_id==STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if(sl->chip_id==STM32_CHIPID_F2) { @@ -398,6 +446,9 @@ char* make_memory_map(stlink_t *sl) { sl->sram_size, sl->flash_size - 0x20000, sl->sys_base, sl->sys_size); + } else if(sl->chip_id==STM32_CHIPID_L4) { + snprintf(map, 4096, memory_map_template_L4, + sl->flash_size, sl->flash_size); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, @@ -516,8 +567,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) return -1; } -#define CODE_BREAK_NUM 6 -#define CODE_LIT_NUM 2 +int code_break_num; +int code_lit_num; +#define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -526,37 +578,41 @@ struct code_hw_breakpoint { int type; }; -struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; +struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); - if (((val & 3) != 1) || - ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || - (((val >> 8) & 0xf) != CODE_LIT_NUM)){ - ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, - ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); - } + code_break_num = ((val >> 4) & 0xf); + code_lit_num = ((val >> 8) & 0xf); + ILOG("Found %i hw breakpoint registers\n", code_break_num); - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); } } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr = addr & ~0x3; - int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + stm32_addr_t fpb_addr; + uint32_t mask; + int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; if(addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return -1; } + if (sl->chip_id==STM32_CHIPID_F7) { + fpb_addr = addr; + } else { + fpb_addr = addr & ~0x3; + } + int id = -1; - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { if(fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; @@ -573,16 +629,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { brk->addr = fpb_addr; - if(set) brk->type |= type; - else brk->type &= ~type; + if (sl->chip_id==STM32_CHIPID_F7) { + if(set) brk->type = type; + else brk->type = 0; + + mask = (brk->addr) | 1; + } else { + if(set) brk->type |= type; + else brk->type &= ~type; + + mask = (brk->addr) | 1 | (brk->type << 30); + } if(brk->type == 0) { DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - uint32_t mask = (brk->addr) | 1 | (brk->type << 30); - DLOG("setting hw break %d at %08x (%d)\n", id, brk->addr, brk->type); DLOG("reg %08x \n", @@ -675,21 +738,24 @@ static int flash_go(stlink_t *sl) { // Some kinds of clock settings do not allow writing to flash. stlink_reset(sl); + stlink_force_debug(sl); for(struct flash_block* fb = flash_root; fb; fb = fb->next) { DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + unsigned length = fb->length - (page - fb->addr); //Update FLASH_PAGE stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - + unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - length > FLASH_PAGE ? FLASH_PAGE : length) < 0) + send) < 0) goto error; + length -= send; + } } @@ -709,6 +775,161 @@ error: return error; } +#define CLIDR 0xE000ED78 +#define CTR 0xE000ED7C +#define CCSIDR 0xE000ED80 +#define CSSELR 0xE000ED84 +#define CCR 0xE000ED14 +#define CCR_DC (1 << 16) +#define CCR_IC (1 << 17) +#define DCCSW 0xE000EF6C +#define ICIALLU 0xE000EF50 + +struct cache_level_desc +{ + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; +}; + +struct cache_desc_t +{ + /* Minimal line size in bytes. */ + unsigned int dminline; + unsigned int iminline; + + /* Last level of unification (uniprocessor). */ + unsigned int louu; + + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; +}; + +static struct cache_desc_t cache_desc; + +/* Return the smallest R so that V <= (1 << R). Not performance critical. */ +static unsigned ceil_log2(unsigned v) +{ + unsigned res; + for (res = 0; (1 << res) < v; res++) + ; + return res; +} + +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) +{ + unsigned int ccsidr; + unsigned int log2_nsets; + ccsidr = stlink_read_debug32(sl, CCSIDR); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +} + +static void init_cache (stlink_t *sl) { + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + /* Assume only F7 has a cache. */ + if(sl->chip_id!=STM32_CHIPID_F7) + return; + + clidr = stlink_read_debug32(sl, CLIDR); + ccr = stlink_read_debug32(sl, CCR); + ctr = stlink_read_debug32(sl, CTR); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for(i = 0; i < 7; i++) + { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if(ct == 2 || ct == 3 || ct == 4) + { + /* Data. */ + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if(ct == 1 || ct == 3) + { + /* Instruction. */ + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } + } +} + +static void cache_flush(stlink_t *sl, unsigned ccr) { + int level; + + if (ccr & CCR_DC) + for (level = cache_desc.louu - 1; level >= 0; level--) + { + struct cache_level_desc *desc = &cache_desc.dcache[level]; + unsigned addr; + unsigned max_addr = 1 << desc->width; + unsigned way_sh = 32 - desc->log2_nways; + + /* D-cache clean by set-ways. */ + for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) + { + unsigned int way; + + for (way = 0; way < desc->nways; way++) + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } + } + + /* Invalidate all I-cache to oPU. */ + if (ccr & CCR_IC) + stlink_write_debug32(sl, ICIALLU, 0); +} + +static int cache_modified; + +static void cache_change(stm32_addr_t start, unsigned count) +{ + if (count == 0) + return; + (void)start; + cache_modified = 1; +} + +static void cache_sync(stlink_t *sl) +{ + unsigned ccr; + + if(sl->chip_id!=STM32_CHIPID_F7) + return; + if (!cache_modified) + return; + cache_modified = 0; + + ccr = stlink_read_debug32(sl, CCR); + if (ccr & (CCR_IC | CCR_DC)) + cache_flush(sl, ccr); +} + int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { @@ -799,7 +1020,9 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { + if(sl->chip_id==STM32_CHIPID_F4 + || sl->chip_id==STM32_CHIPID_F4_HD + || sl->chip_id==STM32_CHIPID_F7) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { @@ -855,6 +1078,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume DLOG("Rcmd: resume\n"); + cache_sync(sl); stlink_run(sl); reply = strdup("OK"); @@ -973,6 +1197,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'c': + cache_sync(sl); stlink_run(sl); while(1) { @@ -1002,6 +1227,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': + cache_sync(sl); stlink_step(sl); reply = strdup("S05"); // TRAP @@ -1156,6 +1382,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); start += align_count; count -= align_count; hexdata += 2*align_count; @@ -1170,6 +1397,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); count -= aligned_count; start += aligned_count; hexdata += 2*aligned_count; @@ -1182,6 +1410,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, count); + cache_change(start, count); } reply = strdup("OK"); break;