X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=gdbserver%2Fgdb-server.c;fp=gdbserver%2Fgdb-server.c;h=eca6597b470d0fae819500d6f1fface020afde30;hb=f782e931b0c51836ffae8a47618e6c2263607555;hp=27b8010293ae368968cf8ecff6c8cd91bf876885;hpb=5121ae07c4a58887dcf940c107a4f45422ffd092;p=fw%2Fstlink diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 27b8010..eca6597 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #ifdef __MINGW32__ @@ -49,6 +48,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +static void init_cache (stlink_t *sl); static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { @@ -173,11 +173,11 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level, 0); + sl = stlink_open_usb(state.logging_level, state.reset, NULL); if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(state.logging_level, 0); + sl = stlink_v1_open(state.logging_level, state.reset); if(sl == NULL) return 1; break; } @@ -185,6 +185,7 @@ int main(int argc, char** argv) { connected_stlink = sl; signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); if (state.reset) { stlink_reset(sl); @@ -208,6 +209,8 @@ int main(int argc, char** argv) { } #endif + init_cache(sl); + do { if (serve(sl, &state)) { sleep (1); // don't go bezurk if serve returns with error @@ -367,6 +370,25 @@ static const char* const memory_map_template_F2 = " " // option byte area ""; +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 KB) + " " // SRAM1 (96 KB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + static const char* const memory_map_template = "" "sram_size, sl->flash_size - 0x20000, sl->sys_base, sl->sys_size); + } else if(sl->chip_id==STM32_CHIPID_L4) { + snprintf(map, 4096, memory_map_template_L4, + sl->flash_size, sl->flash_size); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, @@ -463,11 +488,13 @@ struct code_hw_watchpoint { struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { + uint32_t data; DLOG("init watchpoints\n"); + stlink_read_debug32(sl, 0xE000EDFC, &data); + data |= 1<<24; // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, - stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); + stlink_write_debug32(sl, 0xE000EDFC, data); // make sure all watchpoints are cleared for(int i = 0; i < DATA_WATCH_NUM; i++) { @@ -479,7 +506,7 @@ static void init_data_watchpoints(stlink_t *sl) { static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; - uint32_t mask; + uint32_t mask, dummy; // computer mask // find a free watchpoint @@ -512,7 +539,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16); + stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); return 0; } } @@ -556,9 +583,10 @@ struct code_hw_breakpoint { struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { + unsigned int val; memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); + stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); @@ -727,7 +755,7 @@ static int flash_go(stlink_t *sl) { DLOG("flash_do: page %08x\n", page); unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - send) < 0) + send, 0) < 0) goto error; length -= send; @@ -750,6 +778,162 @@ error: return error; } +#define CLIDR 0xE000ED78 +#define CTR 0xE000ED7C +#define CCSIDR 0xE000ED80 +#define CSSELR 0xE000ED84 +#define CCR 0xE000ED14 +#define CCR_DC (1 << 16) +#define CCR_IC (1 << 17) +#define DCCSW 0xE000EF6C +#define ICIALLU 0xE000EF50 + +struct cache_level_desc +{ + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; +}; + +struct cache_desc_t +{ + /* Minimal line size in bytes. */ + unsigned int dminline; + unsigned int iminline; + + /* Last level of unification (uniprocessor). */ + unsigned int louu; + + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; +}; + +static struct cache_desc_t cache_desc; + +/* Return the smallest R so that V <= (1 << R). Not performance critical. */ +static unsigned ceil_log2(unsigned v) +{ + unsigned res; + for (res = 0; (1U << res) < v; res++) + ; + return res; +} + +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) +{ + unsigned int ccsidr; + unsigned int log2_nsets; + + stlink_read_debug32(sl, CCSIDR, &ccsidr); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +} + +static void init_cache (stlink_t *sl) { + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + /* Assume only F7 has a cache. */ + if(sl->chip_id!=STM32_CHIPID_F7) + return; + + stlink_read_debug32(sl, CLIDR, &clidr); + stlink_read_debug32(sl, CCR, &ccr); + stlink_read_debug32(sl, CTR, &ctr); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for(i = 0; i < 7; i++) + { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if(ct == 2 || ct == 3 || ct == 4) + { + /* Data. */ + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if(ct == 1 || ct == 3) + { + /* Instruction. */ + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } + } +} + +static void cache_flush(stlink_t *sl, unsigned ccr) { + int level; + + if (ccr & CCR_DC) + for (level = cache_desc.louu - 1; level >= 0; level--) + { + struct cache_level_desc *desc = &cache_desc.dcache[level]; + unsigned addr; + unsigned max_addr = 1 << desc->width; + unsigned way_sh = 32 - desc->log2_nways; + + /* D-cache clean by set-ways. */ + for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) + { + unsigned int way; + + for (way = 0; way < desc->nways; way++) + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } + } + + /* Invalidate all I-cache to oPU. */ + if (ccr & CCR_IC) + stlink_write_debug32(sl, ICIALLU, 0); +} + +static int cache_modified; + +static void cache_change(stm32_addr_t start, unsigned count) +{ + if (count == 0) + return; + (void)start; + cache_modified = 1; +} + +static void cache_sync(stlink_t *sl) +{ + unsigned ccr; + + if(sl->chip_id!=STM32_CHIPID_F7) + return; + if (!cache_modified) + return; + cache_modified = 0; + + stlink_read_debug32(sl, CCR, &ccr); + if (ccr & (CCR_IC | CCR_DC)) + cache_flush(sl, ccr); +} + int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { @@ -840,7 +1024,9 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { + if(sl->chip_id==STM32_CHIPID_F4 + || sl->chip_id==STM32_CHIPID_F4_HD + || sl->chip_id==STM32_CHIPID_F7) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { @@ -896,6 +1082,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume DLOG("Rcmd: resume\n"); + cache_sync(sl); stlink_run(sl); reply = strdup("OK"); @@ -1014,6 +1201,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'c': + cache_sync(sl); stlink_run(sl); while(1) { @@ -1043,6 +1231,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': + cache_sync(sl); stlink_step(sl); reply = strdup("S05"); // TRAP @@ -1168,6 +1357,12 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + if (count_rnd > sl->flash_pgsz) + count_rnd = sl->flash_pgsz; + if (count_rnd > 0x1800) + count_rnd = 0x1800; + if (count_rnd < count) + count = count_rnd; stlink_read_mem32(sl, start - adj_start, count_rnd); @@ -1197,6 +1392,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); start += align_count; count -= align_count; hexdata += 2*align_count; @@ -1211,6 +1407,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); count -= aligned_count; start += aligned_count; hexdata += 2*aligned_count; @@ -1223,6 +1420,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, count); + cache_change(start, count); } reply = strdup("OK"); break;