X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Flib%2Fpic%2Flibdev%2Fpic16f870.c;h=780b19957eac04d8ce28e7384f1ce446daac6e3a;hb=13906aff7874da28c033f501fb593bffc2e25dd3;hp=faf7aa18c2398ae3955f55c037a9db6220bfdcbf;hpb=52df981797010227196dd29cd77831d01e1825a8;p=fw%2Fsdcc

diff --git a/device/lib/pic/libdev/pic16f870.c b/device/lib/pic/libdev/pic16f870.c
index faf7aa18..780b1995 100644
--- a/device/lib/pic/libdev/pic16f870.c
+++ b/device/lib/pic/libdev/pic16f870.c
@@ -1,53 +1,53 @@
 /* Register definitions for pic16f870.
  * This file was automatically generated by:
- *   inc2h.pl V1.6
+ *   inc2h.pl V4585
  *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
  */
 #include <pic16f870.h>
 
-data __at (INDF_ADDR) volatile char      INDF;
-sfr  __at (TMR0_ADDR)                    TMR0;
-data __at (PCL_ADDR) volatile char       PCL;
-sfr  __at (STATUS_ADDR)                  STATUS;
-sfr  __at (FSR_ADDR)                     FSR;
-sfr  __at (PORTA_ADDR)                   PORTA;
-sfr  __at (PORTB_ADDR)                   PORTB;
-sfr  __at (PORTC_ADDR)                   PORTC;
-sfr  __at (PCLATH_ADDR)                  PCLATH;
-sfr  __at (INTCON_ADDR)                  INTCON;
-sfr  __at (PIR1_ADDR)                    PIR1;
-sfr  __at (PIR2_ADDR)                    PIR2;
-sfr  __at (TMR1L_ADDR)                   TMR1L;
-sfr  __at (TMR1H_ADDR)                   TMR1H;
-sfr  __at (T1CON_ADDR)                   T1CON;
-sfr  __at (TMR2_ADDR)                    TMR2;
-sfr  __at (T2CON_ADDR)                   T2CON;
-sfr  __at (CCPR1L_ADDR)                  CCPR1L;
-sfr  __at (CCPR1H_ADDR)                  CCPR1H;
-sfr  __at (CCP1CON_ADDR)                 CCP1CON;
-sfr  __at (RCSTA_ADDR)                   RCSTA;
-sfr  __at (TXREG_ADDR)                   TXREG;
-sfr  __at (RCREG_ADDR)                   RCREG;
-sfr  __at (ADRESH_ADDR)                  ADRESH;
-sfr  __at (ADCON0_ADDR)                  ADCON0;
-sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
-sfr  __at (TRISA_ADDR)                   TRISA;
-sfr  __at (TRISB_ADDR)                   TRISB;
-sfr  __at (TRISC_ADDR)                   TRISC;
-sfr  __at (PIE1_ADDR)                    PIE1;
-sfr  __at (PIE2_ADDR)                    PIE2;
-sfr  __at (PCON_ADDR)                    PCON;
-sfr  __at (PR2_ADDR)                     PR2;
-sfr  __at (TXSTA_ADDR)                   TXSTA;
-sfr  __at (SPBRG_ADDR)                   SPBRG;
-sfr  __at (ADRESL_ADDR)                  ADRESL;
-sfr  __at (ADCON1_ADDR)                  ADCON1;
-sfr  __at (EEDATA_ADDR)                  EEDATA;
-sfr  __at (EEADR_ADDR)                   EEADR;
-sfr  __at (EEDATH_ADDR)                  EEDATH;
-sfr  __at (EEADRH_ADDR)                  EEADRH;
-sfr  __at (EECON1_ADDR)                  EECON1;
-sfr  __at (EECON2_ADDR)                  EECON2;
+__sfr  __at (INDF_ADDR)                    INDF;
+__sfr  __at (TMR0_ADDR)                    TMR0;
+__sfr  __at (PCL_ADDR)                     PCL;
+__sfr  __at (STATUS_ADDR)                  STATUS;
+__sfr  __at (FSR_ADDR)                     FSR;
+__sfr  __at (PORTA_ADDR)                   PORTA;
+__sfr  __at (PORTB_ADDR)                   PORTB;
+__sfr  __at (PORTC_ADDR)                   PORTC;
+__sfr  __at (PCLATH_ADDR)                  PCLATH;
+__sfr  __at (INTCON_ADDR)                  INTCON;
+__sfr  __at (PIR1_ADDR)                    PIR1;
+__sfr  __at (PIR2_ADDR)                    PIR2;
+__sfr  __at (TMR1L_ADDR)                   TMR1L;
+__sfr  __at (TMR1H_ADDR)                   TMR1H;
+__sfr  __at (T1CON_ADDR)                   T1CON;
+__sfr  __at (TMR2_ADDR)                    TMR2;
+__sfr  __at (T2CON_ADDR)                   T2CON;
+__sfr  __at (CCPR1L_ADDR)                  CCPR1L;
+__sfr  __at (CCPR1H_ADDR)                  CCPR1H;
+__sfr  __at (CCP1CON_ADDR)                 CCP1CON;
+__sfr  __at (RCSTA_ADDR)                   RCSTA;
+__sfr  __at (TXREG_ADDR)                   TXREG;
+__sfr  __at (RCREG_ADDR)                   RCREG;
+__sfr  __at (ADRESH_ADDR)                  ADRESH;
+__sfr  __at (ADCON0_ADDR)                  ADCON0;
+__sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+__sfr  __at (TRISA_ADDR)                   TRISA;
+__sfr  __at (TRISB_ADDR)                   TRISB;
+__sfr  __at (TRISC_ADDR)                   TRISC;
+__sfr  __at (PIE1_ADDR)                    PIE1;
+__sfr  __at (PIE2_ADDR)                    PIE2;
+__sfr  __at (PCON_ADDR)                    PCON;
+__sfr  __at (PR2_ADDR)                     PR2;
+__sfr  __at (TXSTA_ADDR)                   TXSTA;
+__sfr  __at (SPBRG_ADDR)                   SPBRG;
+__sfr  __at (ADRESL_ADDR)                  ADRESL;
+__sfr  __at (ADCON1_ADDR)                  ADCON1;
+__sfr  __at (EEDATA_ADDR)                  EEDATA;
+__sfr  __at (EEADR_ADDR)                   EEADR;
+__sfr  __at (EEDATH_ADDR)                  EEDATH;
+__sfr  __at (EEADRH_ADDR)                  EEADRH;
+__sfr  __at (EECON1_ADDR)                  EECON1;
+__sfr  __at (EECON2_ADDR)                  EECON2;
 
 // 
 // bitfield definitions
@@ -63,9 +63,15 @@ volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
 volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
 volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
 volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
+volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
+volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
+volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
 volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
 volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
 volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
+volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
+volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
+volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
 volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;