X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Flib%2Fpic%2Flibdev%2Fpic16f684.c;h=b54f92b14e3729a9616d8016925f0ca0ad30c246;hb=4fa52c899d3553b51d56db35d035f17b7e22e66b;hp=c0aaf195c990077589ca9e1d4761e085260d1139;hpb=52df981797010227196dd29cd77831d01e1825a8;p=fw%2Fsdcc

diff --git a/device/lib/pic/libdev/pic16f684.c b/device/lib/pic/libdev/pic16f684.c
index c0aaf195..b54f92b1 100644
--- a/device/lib/pic/libdev/pic16f684.c
+++ b/device/lib/pic/libdev/pic16f684.c
@@ -5,52 +5,52 @@
  */
 #include <pic16f684.h>
 
-data __at (INDF_ADDR) volatile char      INDF;
-sfr  __at (TMR0_ADDR)                    TMR0;
-data __at (PCL_ADDR) volatile char       PCL;
-sfr  __at (STATUS_ADDR)                  STATUS;
-sfr  __at (FSR_ADDR)                     FSR;
-sfr  __at (PORTA_ADDR)                   PORTA;
-sfr  __at (PORTC_ADDR)                   PORTC;
-sfr  __at (PCLATH_ADDR)                  PCLATH;
-sfr  __at (INTCON_ADDR)                  INTCON;
-sfr  __at (PIR1_ADDR)                    PIR1;
-sfr  __at (TMR1L_ADDR)                   TMR1L;
-sfr  __at (TMR1H_ADDR)                   TMR1H;
-sfr  __at (T1CON_ADDR)                   T1CON;
-sfr  __at (TMR2_ADDR)                    TMR2;
-sfr  __at (T2CON_ADDR)                   T2CON;
-sfr  __at (CCPR1L_ADDR)                  CCPR1L;
-sfr  __at (CCPR1H_ADDR)                  CCPR1H;
-sfr  __at (CCP1CON_ADDR)                 CCP1CON;
-sfr  __at (PWM1CON_ADDR)                 PWM1CON;
-sfr  __at (ECCPAS_ADDR)                  ECCPAS;
-sfr  __at (WDTCON_ADDR)                  WDTCON;
-sfr  __at (CMCON0_ADDR)                  CMCON0;
-sfr  __at (CMCON1_ADDR)                  CMCON1;
-sfr  __at (ADRESH_ADDR)                  ADRESH;
-sfr  __at (ADCON0_ADDR)                  ADCON0;
-sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
-sfr  __at (TRISA_ADDR)                   TRISA;
-sfr  __at (TRISC_ADDR)                   TRISC;
-sfr  __at (PIE1_ADDR)                    PIE1;
-sfr  __at (PCON_ADDR)                    PCON;
-sfr  __at (OSCCON_ADDR)                  OSCCON;
-sfr  __at (OSCTUNE_ADDR)                 OSCTUNE;
-sfr  __at (ANSEL_ADDR)                   ANSEL;
-sfr  __at (PR2_ADDR)                     PR2;
-sfr  __at (WPU_ADDR)                     WPU;
-sfr  __at (WPUA_ADDR)                    WPUA;
-sfr  __at (IOC_ADDR)                     IOC;
-sfr  __at (IOCA_ADDR)                    IOCA;
-sfr  __at (VRCON_ADDR)                   VRCON;
-sfr  __at (EEDAT_ADDR)                   EEDAT;
-sfr  __at (EEDATA_ADDR)                  EEDATA;
-sfr  __at (EEADR_ADDR)                   EEADR;
-sfr  __at (EECON1_ADDR)                  EECON1;
-sfr  __at (EECON2_ADDR)                  EECON2;
-sfr  __at (ADRESL_ADDR)                  ADRESL;
-sfr  __at (ADCON1_ADDR)                  ADCON1;
+__data __at (INDF_ADDR) volatile char      INDF;
+__sfr  __at (TMR0_ADDR)                    TMR0;
+__data __at (PCL_ADDR) volatile char       PCL;
+__sfr  __at (STATUS_ADDR)                  STATUS;
+__sfr  __at (FSR_ADDR)                     FSR;
+__sfr  __at (PORTA_ADDR)                   PORTA;
+__sfr  __at (PORTC_ADDR)                   PORTC;
+__sfr  __at (PCLATH_ADDR)                  PCLATH;
+__sfr  __at (INTCON_ADDR)                  INTCON;
+__sfr  __at (PIR1_ADDR)                    PIR1;
+__sfr  __at (TMR1L_ADDR)                   TMR1L;
+__sfr  __at (TMR1H_ADDR)                   TMR1H;
+__sfr  __at (T1CON_ADDR)                   T1CON;
+__sfr  __at (TMR2_ADDR)                    TMR2;
+__sfr  __at (T2CON_ADDR)                   T2CON;
+__sfr  __at (CCPR1L_ADDR)                  CCPR1L;
+__sfr  __at (CCPR1H_ADDR)                  CCPR1H;
+__sfr  __at (CCP1CON_ADDR)                 CCP1CON;
+__sfr  __at (PWM1CON_ADDR)                 PWM1CON;
+__sfr  __at (ECCPAS_ADDR)                  ECCPAS;
+__sfr  __at (WDTCON_ADDR)                  WDTCON;
+__sfr  __at (CMCON0_ADDR)                  CMCON0;
+__sfr  __at (CMCON1_ADDR)                  CMCON1;
+__sfr  __at (ADRESH_ADDR)                  ADRESH;
+__sfr  __at (ADCON0_ADDR)                  ADCON0;
+__sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+__sfr  __at (TRISA_ADDR)                   TRISA;
+__sfr  __at (TRISC_ADDR)                   TRISC;
+__sfr  __at (PIE1_ADDR)                    PIE1;
+__sfr  __at (PCON_ADDR)                    PCON;
+__sfr  __at (OSCCON_ADDR)                  OSCCON;
+__sfr  __at (OSCTUNE_ADDR)                 OSCTUNE;
+__sfr  __at (ANSEL_ADDR)                   ANSEL;
+__sfr  __at (PR2_ADDR)                     PR2;
+__sfr  __at (WPU_ADDR)                     WPU;
+__sfr  __at (WPUA_ADDR)                    WPUA;
+__sfr  __at (IOC_ADDR)                     IOC;
+__sfr  __at (IOCA_ADDR)                    IOCA;
+__sfr  __at (VRCON_ADDR)                   VRCON;
+__sfr  __at (EEDAT_ADDR)                   EEDAT;
+__sfr  __at (EEDATA_ADDR)                  EEDATA;
+__sfr  __at (EEADR_ADDR)                   EEADR;
+__sfr  __at (EECON1_ADDR)                  EECON1;
+__sfr  __at (EECON2_ADDR)                  EECON2;
+__sfr  __at (ADRESL_ADDR)                  ADRESL;
+__sfr  __at (ADCON1_ADDR)                  ADCON1;
 
 // 
 // bitfield definitions