X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Flib%2Fpic%2Flibdev%2Fpic16f648a.c;fp=device%2Flib%2Fpic%2Flibdev%2Fpic16f648a.c;h=32f7009ef12d032687464cc49f63daeb54a17744;hb=52df981797010227196dd29cd77831d01e1825a8;hp=0000000000000000000000000000000000000000;hpb=3671776982c4469774cb43f950143adcfff535f3;p=fw%2Fsdcc

diff --git a/device/lib/pic/libdev/pic16f648a.c b/device/lib/pic/libdev/pic16f648a.c
new file mode 100644
index 00000000..32f7009e
--- /dev/null
+++ b/device/lib/pic/libdev/pic16f648a.c
@@ -0,0 +1,61 @@
+/* Register definitions for pic16f648a.
+ * This file was automatically generated by:
+ *   inc2h.pl V1.6
+ *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
+ */
+#include <pic16f648a.h>
+
+data __at (INDF_ADDR) volatile char      INDF;
+sfr  __at (TMR0_ADDR)                    TMR0;
+data __at (PCL_ADDR) volatile char       PCL;
+sfr  __at (STATUS_ADDR)                  STATUS;
+sfr  __at (FSR_ADDR)                     FSR;
+sfr  __at (PORTA_ADDR)                   PORTA;
+sfr  __at (PORTB_ADDR)                   PORTB;
+sfr  __at (PCLATH_ADDR)                  PCLATH;
+sfr  __at (INTCON_ADDR)                  INTCON;
+sfr  __at (PIR1_ADDR)                    PIR1;
+sfr  __at (TMR1L_ADDR)                   TMR1L;
+sfr  __at (TMR1H_ADDR)                   TMR1H;
+sfr  __at (T1CON_ADDR)                   T1CON;
+sfr  __at (TMR2_ADDR)                    TMR2;
+sfr  __at (T2CON_ADDR)                   T2CON;
+sfr  __at (CCPR1L_ADDR)                  CCPR1L;
+sfr  __at (CCPR1H_ADDR)                  CCPR1H;
+sfr  __at (CCP1CON_ADDR)                 CCP1CON;
+sfr  __at (RCSTA_ADDR)                   RCSTA;
+sfr  __at (TXREG_ADDR)                   TXREG;
+sfr  __at (RCREG_ADDR)                   RCREG;
+sfr  __at (CMCON_ADDR)                   CMCON;
+sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+sfr  __at (TRISA_ADDR)                   TRISA;
+sfr  __at (TRISB_ADDR)                   TRISB;
+sfr  __at (PIE1_ADDR)                    PIE1;
+sfr  __at (PCON_ADDR)                    PCON;
+sfr  __at (PR2_ADDR)                     PR2;
+sfr  __at (TXSTA_ADDR)                   TXSTA;
+sfr  __at (SPBRG_ADDR)                   SPBRG;
+sfr  __at (EEDATA_ADDR)                  EEDATA;
+sfr  __at (EEADR_ADDR)                   EEADR;
+sfr  __at (EECON1_ADDR)                  EECON1;
+sfr  __at (EECON2_ADDR)                  EECON2;
+sfr  __at (VRCON_ADDR)                   VRCON;
+
+// 
+// bitfield definitions
+// 
+volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
+volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
+volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
+volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
+volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
+volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
+volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
+volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
+volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
+volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
+volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
+volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
+