X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Flib%2Fpic%2Flibdev%2Fpic16c71.c;h=d03152023f1533d3a2be6c6de8e876b274b5ea02;hb=d1509cf37c6ba9cc5aa238fcce11824efefc7941;hp=809c3663eef0209402975cde3f4fb69110a5bb38;hpb=52df981797010227196dd29cd77831d01e1825a8;p=fw%2Fsdcc

diff --git a/device/lib/pic/libdev/pic16c71.c b/device/lib/pic/libdev/pic16c71.c
index 809c3663..d0315202 100644
--- a/device/lib/pic/libdev/pic16c71.c
+++ b/device/lib/pic/libdev/pic16c71.c
@@ -1,25 +1,25 @@
 /* Register definitions for pic16c71.
  * This file was automatically generated by:
- *   inc2h.pl V1.6
+ *   inc2h.pl V4514
  *   Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
  */
 #include <pic16c71.h>
 
-data __at (INDF_ADDR) volatile char      INDF;
-sfr  __at (TMR0_ADDR)                    TMR0;
-data __at (PCL_ADDR) volatile char       PCL;
-sfr  __at (STATUS_ADDR)                  STATUS;
-sfr  __at (FSR_ADDR)                     FSR;
-sfr  __at (PORTA_ADDR)                   PORTA;
-sfr  __at (PORTB_ADDR)                   PORTB;
-sfr  __at (ADCON0_ADDR)                  ADCON0;
-sfr  __at (ADRES_ADDR)                   ADRES;
-sfr  __at (PCLATH_ADDR)                  PCLATH;
-sfr  __at (INTCON_ADDR)                  INTCON;
-sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
-sfr  __at (TRISA_ADDR)                   TRISA;
-sfr  __at (TRISB_ADDR)                   TRISB;
-sfr  __at (ADCON1_ADDR)                  ADCON1;
+__data __at (INDF_ADDR) volatile char      INDF;
+__sfr  __at (TMR0_ADDR)                    TMR0;
+__data __at (PCL_ADDR) volatile char       PCL;
+__sfr  __at (STATUS_ADDR)                  STATUS;
+__sfr  __at (FSR_ADDR)                     FSR;
+__sfr  __at (PORTA_ADDR)                   PORTA;
+__sfr  __at (PORTB_ADDR)                   PORTB;
+__sfr  __at (ADCON0_ADDR)                  ADCON0;
+__sfr  __at (ADRES_ADDR)                   ADRES;
+__sfr  __at (PCLATH_ADDR)                  PCLATH;
+__sfr  __at (INTCON_ADDR)                  INTCON;
+__sfr  __at (OPTION_REG_ADDR)              OPTION_REG;
+__sfr  __at (TRISA_ADDR)                   TRISA;
+__sfr  __at (TRISB_ADDR)                   TRISB;
+__sfr  __at (ADCON1_ADDR)                  ADCON1;
 
 // 
 // bitfield definitions
@@ -28,5 +28,9 @@ volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
 volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
 volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
 volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
+volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
+volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
 volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
+volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
+volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;