X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Flib%2Fpic%2Flibdev%2Fpic16c433.c;fp=device%2Flib%2Fpic%2Flibdev%2Fpic16c433.c;h=e8e1b6f5eaae6e6873fcc383bd21aac6a0da35bd;hb=52df981797010227196dd29cd77831d01e1825a8;hp=0000000000000000000000000000000000000000;hpb=3671776982c4469774cb43f950143adcfff535f3;p=fw%2Fsdcc diff --git a/device/lib/pic/libdev/pic16c433.c b/device/lib/pic/libdev/pic16c433.c new file mode 100644 index 00000000..e8e1b6f5 --- /dev/null +++ b/device/lib/pic/libdev/pic16c433.c @@ -0,0 +1,38 @@ +/* Register definitions for pic16c433. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (GPIO_ADDR) GPIO; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISIO_ADDR) TRISIO; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCAL_ADDR) OSCCAL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +