X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Finclude%2Fpic%2Fpic12f629.h;h=cee2c2954a4f96d92bc85f5a96130b137e87466c;hb=d1509cf37c6ba9cc5aa238fcce11824efefc7941;hp=4015b5e26ace970d8f2a5c69265b590e92a54373;hpb=14fbdef91206e1fa14b6fedf1b013cbba1021124;p=fw%2Fsdcc diff --git a/device/include/pic/pic12f629.h b/device/include/pic/pic12f629.h index 4015b5e2..cee2c295 100644 --- a/device/include/pic/pic12f629.h +++ b/device/include/pic/pic12f629.h @@ -4,7 +4,7 @@ // // This header file was automatically generated by: // -// inc2h.pl V1.7 +// inc2h.pl V4514 // // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved // @@ -163,7 +163,7 @@ extern __sfr __at (EECON2_ADDR) EECON2; //----- T1CON Bits --------------------------------------------------------- -//----- CMCON Bits -------------------------------------------------------- +//----- COMCON Bits -------------------------------------------------------- //----- OPTION Bits -------------------------------------------------------- @@ -251,6 +251,26 @@ extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; #define CINV CMCON_bits.CINV #define COUT CMCON_bits.COUT +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + // ----- GPIO bits -------------------- typedef union { struct { @@ -542,27 +562,13 @@ typedef union { unsigned char :1; unsigned char VREN:1; }; - struct { - unsigned char RD:1; - unsigned char WR:1; - unsigned char WREN:1; - unsigned char WRERR:1; - unsigned char :1; - unsigned char :1; - unsigned char :1; - unsigned char :1; - }; } __VRCON_bits_t; extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; #define VR0 VRCON_bits.VR0 -#define RD VRCON_bits.RD #define VR1 VRCON_bits.VR1 -#define WR VRCON_bits.WR #define VR2 VRCON_bits.VR2 -#define WREN VRCON_bits.WREN #define VR3 VRCON_bits.VR3 -#define WRERR VRCON_bits.WRERR #define VRR VRCON_bits.VRR #define VREN VRCON_bits.VREN