X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=device%2Finclude%2Fmcs51reg.h;h=ad156ca55ae3b53adb010ceaf6fcba8e7155a690;hb=bc04edccb1ca8d1dafb8ae5c96b047005029b866;hp=cda73026cf28d4b8657e8df1f3fd3341c0c32292;hpb=23f3f050c932c7365f9331c26572ff20ddb0165d;p=fw%2Fsdcc diff --git a/device/include/mcs51reg.h b/device/include/mcs51reg.h index cda73026..ad156ca5 100644 --- a/device/include/mcs51reg.h +++ b/device/include/mcs51reg.h @@ -34,36 +34,78 @@ Version 1.0.2 (Nov 6, 2000) T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs - Support for for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55 - Support for the Dallas DS80C320 and DS80C323 microcontrollers - microcontrollers - B. Torok / bela.torok@kssg.ch + Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55 + Support for the Dallas DS80C320 and DS80C323 + B. Torok / bela.torok@kssg.ch Version 1.0.3 (Nov 7, 2000) SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch + Version 1.0.4 (Nov 9, 2000) + To simplify the identication of registers, a large number of definitios + were renamed. Long register names now (hopefully) clearly define the + function of the registers. + Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch + + Version 1.0.5 (Dec 15, 2000) + Definitions added: #ifdef MCS51REG_EXTERNAL_ROM + #ifdef MCS51REG_EXTERNAL_RAM + #ifndef MCS51REG_DISABLE_WARNINGS + + + Version 1.0.6 (March 10, 2001) + Support for the Dallas DS5000 & DS2250 + Support for the Dallas DS5001 & DS2251 + Support for the Dallas DS80C390 + microcontrollers - B. Torok / bela.torok@kssg.ch + + Version 1.0.7 (June 7, 2001) + #ifndef MCS51REG_DISABLE_WARNINGS removed + #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch + Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de + + Version 1.0.8 (Feb 28, 2002) + Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch + Revised by lanius@ewetel.net + + Version 1.0.9 (Sept 9, 2002) + Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de + + Version 1.0.10 (Sept 19, 2002) + Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net + Adding support for additional microcontrollers: ----------------------------------------------- - 1. Make an entry with the inventory of the register set of - the microcontroller in the "Describe microcontrollers" section. + 1. Don't modify this file!!! + + 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include + this after the #define HEADER_MCS51REG statement in this file + + 3. The mcs51reg_update.h file should contain following definitions: - 2. If necessary add/modify entry(s) in the "Register definitions" section + a. An entry with the inventory of the register set of the + microcontroller in the "Describe microcontrollers" section. - 3. If necessary add/modify entry(s) in the "Interrupt vectors" section + b. If necessary add entry(s) for registers not defined in this file - 4. Make a step-by-step protocol of your modifications + c. Define interrupt vectors - 5. Send the protocol and the modified file to me ( bela.torok@kssg.ch ). - I'm going to compile/verify changes made by different authors. + 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:, + sdcc -E test.c > t.txt + and check definitions for validity in the t.txt file. + + 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch + I'm going to resolve conflicts & verify/merge new definitions to this file. Microcontroller support: Use one of the following options: - 1. use #include in your program & define REG_XXXXXX in your makefile. + 1. use #include in your program & define MICROCONTROLLER_XXXX in your makefile. 2. use following definitions prior the #include line in your program: @@ -84,11 +126,30 @@ MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers + MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller + MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers + MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller + MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers + MICROCONTROLLER_P80C552 Philips P80C552 + MICROCONTROLLER_P89C668 Philips P89C668 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517 + MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2 + + Additional definitions (use them prior the #include mcs51reg.h statement): + + Ports P0 & P2 are not available for the programmer if external ROM used. + Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2. + + Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if + external RAM is used. + Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2, + P3_6, WR, P3_7 & RD. + + #define MCS51REG_ENABLE_WARNINGS -> enable warnings -----------------------------------------------------------------------*/ @@ -96,6 +157,12 @@ #ifndef HEADER_MCS51REG #define HEADER_MCS51REG +/////////////////////////////////////////////////////// +/// Insert header here (for developers only) /// +/// remove "//" from the begining of the next line /// +//#include "mcs51reg_update.h" /// +/////////////////////////////////////////////////////// + ////////////////////////////////// /// Describe microcontrollers /// /// (inventory of registers) /// @@ -109,12 +176,14 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: 8051 +#endif #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -125,9 +194,9 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__x__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B @@ -143,13 +212,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: 8052 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -160,15 +231,14 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_8052 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 @@ -186,12 +256,14 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Atmel AT89Cx051 +#endif // 8051 register set without P0 & P2 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -201,9 +273,9 @@ #define P1 #define SCON #define SBUF -#define IE +#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__x__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B @@ -220,13 +292,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: AT89S53 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -237,22 +311,21 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_8052 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 #define TH2 // AT89S53 specific register -#define T2MOD -#define IP_EXT_AT89X52_55 +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__x__x__x__x__x__x__T2EX__T2 #define SPCR #define SPDR #define SPSR @@ -271,13 +344,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: AT89C52 or AT89LV52 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -288,22 +363,21 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_8052 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 #define TH2 -// AT89X52 specific register -#define T2MOD -#define IP_EXT_AT89X52_55 +// AT89X55 specific register +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__x__x__x__x__x__x__T2EX__T2 #endif // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers @@ -316,13 +390,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: AT89C55 or AT89LV55 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -333,26 +409,107 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_8052 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 #define TH2 -// AT89X52 specific register -#define T2MOD -#define IP_EXT_AT89X52_55 +// AT89X55 specific register +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__x__x__x__x__x__x__T2EX__T2 #endif // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers +// definitions for the Dallas DS5000 +#ifdef MICROCONTROLLER_DS5000 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: DS5000 +#endif +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SBUF +#define P2 +#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 +#define P3 +#define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 +#define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3 +#define TA +#define PSW +#define ACC +#define B +#endif +// end of definitions for the Dallas DS5000 + + +// definitions for the Dallas DS5001 +#ifdef MICROCONTROLLER_DS5001 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: DS5001 +#endif +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SBUF +#define P2 +#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 +#define P3 +#define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 +#define CRC +#define CRCLOW +#define CRCHIGH +#define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL +#define TA +#define RNR +#define PSW +#define RPCTL +#define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF +#define ACC +#define B +#endif +// end of definitions for the Dallas DS5001 + + // definitions for the Dallas DS80C320 and DS80C323 microcontrollers #ifdef MICROCONTROLLER_DS80C32X #ifdef MICROCONTROLLER_DEFINED @@ -361,13 +518,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Dallas DS80C320 or DS80C323 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE #define TCON #define TMOD #define TL0 @@ -376,46 +535,242 @@ #define TH1 #define P1 #define SCON +#define SCON0 #define SBUF #define P2 -#define IE +#define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_80C320 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 #define TH2 // DS80C320 specific register -#define P1_EXT_DS80C320 -#define IP_EXT_DS80C320 -#define PCON_EXT_DS8XCX2X #define DPL1 #define DPH1 -#define DPS -#define CKCON -#define EXIF_DS80C32X +#define DPS__x__x__x__x__x__x__x__SEL +#define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +#define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS #define SADDR0 #define SADDR1 #define SADEN0 #define SADEN1 #define SCON1 #define SBUF1 -#define STATUS_DS80C32X +#define STATUS__PIP__HIP__LIP__x__x__x__x__x #define TA -#define T2MOD +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 #define WDCON -#define EIE -#define EIP +#define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 +#define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 #endif // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers +// definitions for the Dallas DS80C390 +#ifdef MICROCONTROLLER_DS80C390 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: Dallas DS80C390 +#endif +// 8051 register set +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SCON0 +#define SBUF +#define P2 +#define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 +#define P3 +#define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 +#define PSW +#define ACC +#define B +// 8052 specific registers +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#define RCAP2L +#define RCAP2H +#define TL2 +#define TH2 +// DS80C390 specific register +#define P4_AT_0X80 +#define DPL1 +#define DPH1 +#define DPS__ID1__ID0__TSL__x__x__x__x__SEL +#define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +#define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS +#define P4CNT +#define DPX +#define DPX1 +#define C0RMS0 +#define C0RMS1 +#define ESP +#define AP +#define ACON__x__x__x__x__x__SA__AM1__AM0 +#define C0TMA0 +#define C0TMA1 +#define P5_AT_0XA1 +#define P5CNT +#define C0C +#define C0S +#define C0IR +#define C0TE +#define C0RE +#define SADDR0 +#define SADDR1 +#define C0M1C +#define C0M2C +#define C0M3C +#define C0M4C +#define C0M5C +#define C0M6C +#define C0M7C +#define C0M8C +#define C0M9C +#define C0M10C +#define SADEN0 +#define SADEN1 +#define C0M11C +#define C0M12C +#define C0M13C +#define C0M14C +#define C0M15C +#define SCON1 +#define SBUF1 +#define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x +#define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 +#define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 +#define TA +#define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN +#define COR +#define MCNT0 +#define MCNT1 +#define MA +#define MB +#define MC +#define C1RSM0 +#define C1RSM1 +#define WDCON +#define C1TMA0 +#define C1TMA1 +#define C1C +#define C1S +#define C1IR +#define C1TE +#define C1RE +#define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 +#define MXMAX +#define C1M1C +#define C1M2C +#define C1M3C +#define C1M4C +#define C1M5C +#define C1M6C +#define C1M7C +#define C1M8C +#define C1M9C +#define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 +#define C1M10C +#define C1M11C +#define C1M12C +#define C1M13C +#define C1M14C +#define C1M15C +#define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 +#endif +// end of definitions for the Dallas DS80C390 + +// definitions for the Dallas DS89C420 microcontroller +#ifdef MICROCONTROLLER_DS89C420 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: Dallas DS89C420 +#endif +// 8051 register set +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SCON0 +#define SBUF +#define P2 +#define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 +#define P3 +#define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 +#define PSW +#define ACC +#define B +// 8052 specific registers +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#define RCAP2L +#define RCAP2H +#define TL2 +#define TH2 +// DS8XC420 specific registers +#define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x +#define DPL1 +#define DPH1 +#define DPS__ID1__ID0__TSL__AID__x__x__x__SEL +#define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +#define CKMOD +#define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 +#define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 +#define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS +#define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 +#define SADDR0 +#define SADDR1 +#define SADEN0 +#define SADEN1 +#define SCON1 +#define SBUF1 +#define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 +#define TA +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 +#define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 +#define WDCON +#define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 +#define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 +#define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 +#define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 +#endif +// end of definitions for the Dallas DS89C420 microcontroller + // definitions for the Dallas DS87C520 and DS83C520 microcontrollers #ifdef MICROCONTROLLER_DS8XC520 #ifdef MICROCONTROLLER_DEFINED @@ -424,13 +779,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Dallas DS87C520 or DS85C520 +#endif // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE #define TCON #define TMOD #define TL0 @@ -439,49 +796,205 @@ #define TH1 #define P1 #define SCON +#define SCON0 #define SBUF #define P2 -#define IE +#define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 #define P3 -#define IP +#define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 #define PSW #define ACC #define B // 8052 specific registers -#define IE_EXT_80C320 -#define T2CON +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 #define RCAP2L #define RCAP2H #define TL2 #define TH2 // DS8XC520 specific registers -#define P1_EXT_DS80C320 -#define IP_EXT_DS80C320 -#define PCON_EXT_DS8XCX2X #define DPL1 #define DPH1 -#define DPS -#define CKCON -#define EXIF_DS8XC520 -#define PMR +#define DPS__x__x__x__x__x__x__x__SEL +#define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +#define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS +#define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 #define SADDR0 #define SADDR1 #define SADEN0 #define SADEN1 #define SCON1 #define SBUF1 -#define STATUS_DS80C32X +#define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 #define TA -#define T2MOD +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 #define WDCON -#define ROMSIZE +#define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 +#define BP2 #define WDCON -#define EIE -#define EIP +#define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 +#define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 #endif // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers +// definitions for the Philips P80C552 microcontroller +#ifdef MICROCONTROLLER_P80C552 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: Philips P80C552 +#endif +// 8051 register set +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SBUF +#define P2 +#define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 +#define P3 +#define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 +#define PSW +#define ACC +#define B +// P80C552 specific register-names +#define S0BUF // same as SBUF, set in mcs51reg.h +#define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI +// P80C552 specific registers +#define ADCH_AT_0XC6 +#define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 +#define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 +#define CTH0_AT_0XCC +#define CTH1_AT_0XCD +#define CTH2_AT_0XCE +#define CTH3_AT_0XCF +#define CMH0_AT_0XC9 +#define CMH1_AT_0XCA +#define CMH2_AT_0XCB +#define CTL0_AT_0XAC +#define CTL1_AT_0XAD +#define CTL2_AT_0XAE +#define CTL3_AT_0XAF +#define CML0_AT_0XA9 +#define CML1_AT_0XAA +#define CML2_AT_0XAB +#define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 +#define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 +#define PWM0_AT_0XFC +#define PWM1_AT_0XFD +#define PWMP_AT_0XFE +#define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I +#define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 +#define P5_AT_0XC4 +#define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 +#define S1ADR__x__x__x__x__x__x__x__GC +#define S1DAT_AT_0XDA +#define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x +#define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 +#define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 +#define TMH2_AT_0XED +#define TML2_AT_0XEC +#define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 +#define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 +#define T3_AT_0XFF +#endif +// end of definitions for the Philips P80C552 microcontroller + + +// definitions for the Philips P89C668 +#ifdef MICROCONTROLLER_P89C668 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: P89C668 +#endif +#define P0 +#define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +#define P1 +#define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +#define P2 +#define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +#define P3 +#define P3_EXT__x__x__CEX4__CEX3__x__x__x__x +#define SP +#define DPL +#define DPH +#define TCON +#define TMOD +#define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define SCON +#define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI +#define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 +#define SBUF +#define S0BUF SBUF +#define PSW +#define ACC +#define B +#define SADR_AT_0XA9 +#define SADEN_AT_0XB9 +#define S1IST_AT_0XDC +#define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x +#define S1DAT_AT_0XDA +#define S1ADR__x__x__x__x__x__x__x__GC +#define SBUF +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define RCAP2L +#define RCAP2H +#define TL2 +#define TH2 +#define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +#define IEN1__x__x__x__x__x__x__x__ET2 +#define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +#define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +#define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +#define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#define AUXR__x__x__x__x__x__x__EXTRAM__A0 +#define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +#define WDTRST_AT_0XA6 +#define CCAPM0_AT_0XC2 +#define CCAPM1_AT_0XC3 +#define CCAPM2_AT_0XC4 +#define CCAPM3_AT_0XC5 +#define CCAPM4_AT_0XC6 +#define CCAP0L_AT_0XEA +#define CCAP1L_AT_0XEB +#define CCAP2L_AT_0XEC +#define CCAP3L_AT_0XED +#define CCAP4L_AT_0XEE +#define CH_AT_0XF9 +#define CL_AT_0XE9 +#define CCAP0H_AT_0XFA +#define CCAP1H_AT_0XFB +#define CCAP2H_AT_0XFC +#define CCAP3H_AT_0XFD +#define CCAP4H_AT_0XFE +#endif +// end of definitions for the Philiüs P89C668 + + // definitions for the Infineon / Siemens SAB80515 & SAB80535 #ifdef MICROCONTROLLER_SAB80515 #ifdef MICROCONTROLLER_DEFINED @@ -490,12 +1003,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535 -// 8051 register set without IP & PCON +#endif +// 8051 register set without IP #define P0 #define SP #define DPL #define DPH +#define PCON__SMOD__x__x__x__x__x__x__x #define TCON #define TMOD #define TL0 @@ -506,35 +1022,33 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 #define P3 #define PSW #define ACC #define B // SAB80515 specific registers -#define IE_EXT_SAB80515X // Definitions for additional Bit registers -#define P1_EXT_SAB80515X // P1 alternate functions - SAB80515 specific -#define PCON_80515 // PCON - SAB80515 specific -#define IP0 // interrupt priority register - SAB80515 specific -#define IEN1 // interrupt enable register - SAB80515 specific -#define IRCON // interrupt control register - SAB80515 specific -#define CCEN // compare/capture enable register -#define CCL1 // compare/capture register 1, low byte -#define CCH1 // compare/capture register 1, high byte -#define CCL2 // compare/capture register 2, low byte -#define CCH2 // compare/capture register 2, high byte -#define CCL3 // compare/capture register 3, low byte -#define CCH3 // compare/capture register 3, high byte -#define T2CON_SABX -#define CRCL // compare/reload/capture register, low byte -#define CRCH // compare/reload/capture register, high byte +#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 +#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 +#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC +#define IRCON +#define CCEN +#define CCL1 +#define CCH1 +#define CCL2 +#define CCH2 +#define CCL3 +#define CCH3 +#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 +#define CRCL +#define CRCH #define TL2 #define TH2 -#define ADCON // A/D-converter control register -#define ADDAT // A/D-converter data register -#define DAPR_SAB80515 // D/A-converter program register -#define P4_SAB80515 // Port 4 - SAB80515 specific -#define P5_SAB80515 // Port 5 - SAB80515 specific +#define ADCON +#define ADDAT +#define DAPR__SAB80515 +#define P4_AT_0XE8 +#define P5_AT_0XF8 #endif // end of definitions for the Infineon / Siemens SAB80515 @@ -547,13 +1061,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Infineon / Siemens SAB80515A +#endif // 8051 register set without IP #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL #define TCON #define TMOD #define TL0 @@ -564,42 +1080,40 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 #define P3 #define PSW #define ACC #define B // SAB80515A specific registers -#define IE_EXT_SAB80515X // Definitions for additional Bit registers -#define P1_EXT_SAB80515X // P1 alternate functions - SAB80515 specific -#define PCON_EXT_80515A // Definitions for additional Bit registers -#define IP0 // interrupt priority register - SAB80515 specific -#define IP1 // interrupt priority register - SAB80515 specific -#define IEN1 // interrupt enable register - SAB80515 specific -#define IRCON // interrupt control register - SAB80515 specific -#define CCEN // compare/capture enable register -#define CCL1 // compare/capture register 1, low byte -#define CCH1 // compare/capture register 1, high byte -#define CCL2 // compare/capture register 2, low byte -#define CCH2 // compare/capture register 2, high byte -#define CCL3 // compare/capture register 3, low byte -#define CCH3 // compare/capture register 3, high byte -#define T2CON_SABX -#define CRCL // compare/reload/capture register, low byte -#define CRCH // compare/reload/capture register, high byte +#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 +#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 +#define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 +#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC +#define IRCON +#define CCEN +#define CCL1 +#define CCH1 +#define CCL2 +#define CCH2 +#define CCL3 +#define CCH3 +#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 +#define CRCL +#define CRCH #define TL2 #define TH2 -#define ADCON0 // A/D-converter control register 0 -#define ADDATH // A/D data high byte -#define ADDATL // A/D data low byte -#define ADCON1 // A/D-converter control register 1 -#define SRELL // Baudrate generator reload low -#define SYSCON // XRAM Controller Access Control -#define SRELH // Baudrate generator reload high -#define P4_SAB80515 // Port 4 - SAB80515 specific -#define P5_SAB80515 // Port 5 - SAB80515 specific -#define P6_SAB80515 // Port 6 - SAB80515 specific -#define XPAGE // Page Address Register for Extended On-Chip RAM +#define ADCON0 +#define ADDATH +#define ADDATL +#define ADCON1 +#define SRELL +#define SYSCON +#define SRELH +#define P4_AT_0XE8 +#define P5_AT_0XF8 +#define P6_AT_0XDB +#define XPAGE #endif // end of definitions for the Infineon / Siemens SAB80515A @@ -612,13 +1126,15 @@ #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED #endif +#ifdef MCS51REG_ENABLE_WARNINGS #warning Selected HW: Infineon / Siemens SAB80517 +#endif // 8051 register set without IP, SCON & SBUF #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL #define TCON #define TMOD #define TL0 @@ -629,115 +1145,104 @@ // #define SCON // #define SBUF #define P2 -#define IE +#define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 #define P3 #define PSW #define ACC #define B // SAB80517 specific registers -#define IE_EXT_SAB80515X // Definitions for additional Bit registers -#define P1_EXT_SAB80515X // P1 alternate functions - SAB80515 specific -#define PCON_EXT_80515A // Definitions for additional Bit registers -#define IP0 // interrupt priority register - SAB80517 specific -#define IP1 // interrupt priority register - SAB80517 specific -#define IEN1 // interrupt enable register - SAB80517 specific -#define IEN2_SAB80517 // interrupt enable register 2 - SAB80517 specific -#define IRCON // interrupt control register - SAB80517 specific -#define CCEN // compare/capture enable register -#define CCL1 // compare/capture register 1, low byte -#define CCH1 // compare/capture register 1, high byte -#define CCL2 // compare/capture register 2, low byte -#define CCH2 // compare/capture register 2, high byte -#define CCL3 // compare/capture register 3, low byte -#define CCH3 // compare/capture register 3, high byte -#define CCL4 // compare/capture register 4, low byte -#define CCH4 // compare/capture register 4, high byte -#define CC4EN // compare/capture register 4 enable -#define CMEN // compare enable register -#define CMH0 // compare register 0, high byte -#define CML0 // compare register 0, low byte -#define CMH1 // compare register 1, high byte -#define CML1 // compare register 1, low byte -#define CMH2 // compare register 2, high byte -#define CML2 // compare register 2, low byte -#define CMH3 // compare register 3, high byte -#define CML3 // compare register 3, low byte -#define CMH4 // compare register 4, high byte -#define CML4 // compare register 4, low byte -#define CMH5 // compare register 5, high byte -#define CML5 // compare register 5, low byte -#define CMH6 // compare register 6, high byte -#define CML6 // compare register 6, low byte -#define CMH7 // compare register 7, high byte -#define CML7 // compare register 7, low byte -#define CMSEL // compare input select -#define T2CON_SABX -#define CRCL // compare/reload/capture register, low byte -#define CRCH // compare/reload/capture register, high byte -#define CTCON // com.timer control register -#define CTRELH // com.timer rel register high byte -#define CTRELL // com.timer rel register low byte +#define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 +#define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 +#define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 +#define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC +#define IEN2__SAB80517 +#define IRCON +#define CCEN +#define CCL1 +#define CCH1 +#define CCL2 +#define CCH2 +#define CCL3 +#define CCH3 +#define CCL4 +#define CCH4 +#define CC4EN +#define CMEN +#define CMH0 +#define CML0 +#define CMH1 +#define CML1 +#define CMH2 +#define CML2 +#define CMH3 +#define CML3 +#define CMH4 +#define CML4 +#define CMH5 +#define CML5 +#define CMH6 +#define CML6 +#define CMH7 +#define CML7 +#define CMSEL +#define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 +#define CRCL +#define CRCH +#define CTCOM_AT_0XE1 +#define CTRELH +#define CTRELL #define TL2 #define TH2 -#define ADCON0 // A/D-converter control register 0 -#define ADCON1 // A/D-converter control register 1 -#define ADDAT // A/D-converter data register -#define DAPR_SAB80517 // D/A-converter program register -#define P4_SAB80515 // Port 4 - SAB80515 specific -#define P5_SAB80515 // Port 5 - SAB80515 specific -#define P6_SAB80517 // Port 6 - SAB80517 specific -#define P7_SAB80517 // Port 7 - SAB80517 specific -#define P8_SAB80517 // Port 8 - SAB80517 specific -#define DPSEL // data pointer select register -#define ARCON // Arithmetic Ctrl. Register -#define MD0 // MUL / DIV register 0 -#define MD1 // MUL / DIV register 1 -#define MD2 // MUL / DIV register 2 -#define MD3 // MUL / DIV register 3 -#define MD4 // MUL / DIV register 4 -#define MD5 // MUL / DIV register 5 -#define S0BUF // serial 0 buffer register -#define S0CON // serial 0 control register -#define S0RELH // serial 0 reload register high byte -#define S0RELL // serial 0 reload register low byte -#define S1BUF // serial 0 buffer register -#define S1CON // serial 0 control register -#define S1RELH // serial 0 reload register high byte -#define S1RELL // serial 0 reload register low byte -#define WDTH // watchdog timer high byte -#define WDTL // watchdog timer low byte -#define WDTREL // watchdog timer reload register +#define ADCON0 +#define ADCON1 +#define ADDAT +#define DAPR__SAB80517 +#define P4_AT_0XE8 +#define P5_AT_0XF8 +#define P6_AT_0XFA +#define P7_AT_0XDB +#define P8_AT_0XDD +#define DPSEL +#define ARCON +#define MD0 +#define MD1 +#define MD2 +#define MD3 +#define MD4 +#define MD5 +#define S0BUF +#define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 +#define S0RELH +#define S0RELL +#define S1BUF +#define S1CON_AT_0X9B +#define S1RELH +#define S1RELL +#define WDTH +#define WDTL +#define WDTREL #endif // end of definitions for the Infineon / Siemens SAB80517 -///////////////////////////////////////////////////////// -/// don't specify microcontrollers below this line! /// -///////////////////////////////////////////////////////// - - -// default microcontroller -> 8051 -// use default if no microcontroller specified +// definitions for the Atmel T89C51RD2 +#ifdef MICROCONTROLLER_T89C51RD2 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif #ifndef MICROCONTROLLER_DEFINED #define MICROCONTROLLER_DEFINED -#warning ////////////////////////////////// -#warning // No microcontroller defined! // -#warning ////////////////////////////////// -#warning Code will be generated for the -#warning 8051 (default) microcontroller. -#warning If you have another microcontroller -#warning define it in the makefile, or in the -#warning "C" source prior -#warning the #include statement. -#warning If you use a non supported -#warning microcontroller, mcs51reg.h can be -#warning easily extended to support your HW. +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: T89C51RD2 +#endif + // 8051 register set #define P0 #define SP #define DPL #define DPH -#define PCON +#define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL #define TCON #define TMOD #define TL0 @@ -748,30 +1253,160 @@ #define SCON #define SBUF #define P2 -#define IE +#define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 +#define SADDR #define P3 -#define IP +#define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 #define PSW #define ACC #define B -#endif -// end of definitions for the default microcontroller +// 8052 register set +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#define RCAP2L +#define RCAP2H +#define TL2 +#define TH2 -#ifdef MCS51REG_ERROR -#error Two or more microcontrollers defined! -#endif +// T89C51RD2 register set +#define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 +#define P5_AT_0XE8 +#define SADEN0 + +#define AUXR1__x__x__x__x__GF3__x__x__DPS +#define WDTRST_AT_0XA6 +#define WDTPRG_AT_0XA7 +#define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 +#define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H +#define FCON +#define EECON +#define EETIM +#define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x +#define CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 +#define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#define CCAPM0_AT_0XDA +#define CCAPM1_AT_0XDB +#define CCAPM2_AT_0XDC +#define CCAPM3_AT_0XDD +#define CCAPM4_AT_0XDE +#define CL_AT_0XE9 +#define CCAP0L_AT_0XEA +#define CCAP1L_AT_0XEB +#define CCAP2L_AT_0XEC +#define CCAP3L_AT_0XED +#define CCAP4L_AT_0XEE +#define CH_AT_0XF9 +#define CCAP0H_AT_0XFA +#define CCAP1H_AT_0XFB +#define CCAP2H_AT_0XFC +#define CCAP3H_AT_0XFD +#define CCAP4H_AT_0XFE +#endif /* MICROCONTROLLER_T89C51RD2 */ +/* end of definition for the Atmel T89C51RD2 */ + + +///////////////////////////////////////////////////////// +/// don't specify microcontrollers below this line! /// +///////////////////////////////////////////////////////// + + +// default microcontroller -> 8051 +// use default if no microcontroller specified +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#ifdef MCS51REG_ENABLE_WARNINGS +#warning No microcontroller defined! +#warning Code generated for the 8051 +#endif +// 8051 register set +#define P0 +#define SP +#define DPL +#define DPH +#define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL +#define TCON +#define TMOD +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define P1 +#define SCON +#define SBUF +#define P2 +#define IE__EA__x__x__ES__ET1__EX1__ET0__EX0 +#define P3 +#define IP__x__x__x__PS__PT1__PX1__PT0__PX0 +#define PSW +#define ACC +#define B +#endif +// end of definitions for the default microcontroller + + +#ifdef MCS51REG_ERROR +#error Two or more microcontrollers defined! +#endif + +#ifdef MCS51REG_EXTERNAL_ROM +#ifndef MCS51REG_UNDEFINE_P0 +#define MCS51REG_UNDEFINE_P0 +#endif +#ifndef MCS51REG_UNDEFINE_P2 +#define MCS51REG_UNDEFINE_P2 +#endif +#endif + +#ifdef MCS51REG_EXTERNAL_RAM +#ifndef MCS51REG_UNDEFINE_P0 +#define MCS51REG_UNDEFINE_P0 +#endif +#ifndef MCS51REG_UNDEFINE_P2 +#define MCS51REG_UNDEFINE_P2 +#endif +#endif + +#ifdef MCS51REG_UNDEFINE_P0 +#undef P0 +#endif + +#ifdef MCS51REG_UNDEFINE_P2 +#undef P2 +#endif //////////////////////////////// -/// Register definitions /// -/// (In alphabetical order) /// -//////////////////////////////// +/// Register definitions /// +/// (In alphabetical order) /// +//////////////////////////////// #ifdef ACC #undef ACC sfr at 0xE0 ACC ; #endif +#ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x +#undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x +sfr at 0x9D ACON ; // DS89C420 specific +// Not directly accessible bits +#define PAGES0 0x20 +#define PAGES1 0x40 +#define PAGEE 0x80 +#endif + +#ifdef ACON__x__x__x__x__x__SA__AM1__AM0 +#undef ACON__x__x__x__x__x__SA__AM1__AM0 +sfr at 0x9D ACON ; // DS89C390 specific +// Not directly accessible bits +#define AM0 0x01 +#define AM1 0x02 +#define SA 0x04 +#endif + +#ifdef ADCH_AT_0XC6 +#undef ADCH_AT_0XC6 +sfr at 0xC6 ADCH ; // A/D converter high +#endif + #ifdef ADCON #undef ADCON sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific @@ -799,24 +1434,38 @@ sbit at 0xDD ADEX ; sbit at 0xDE CLK ; sbit at 0xDF BD ; // Not directly accessible ADCON0 -#define ADCON0_MX0 0x01 -#define ADCON0_MX1 0x02 -#define ADCON0_MX2 0x04 -#define ADCON0_ADM 0x08 -#define ADCON0_BSY 0x10 -#define ADCON0_ADEX 0x20 -#define ADCON0_CLK 0x40 -#define ADCON0_BD 0x80 +#define ADCON0_MX0 0x01 +#define ADCON0_MX1 0x02 +#define ADCON0_MX2 0x04 +#define ADCON0_ADM 0x08 +#define ADCON0_BSY 0x10 +#define ADCON0_ADEX 0x20 +#define ADCON0_CLK 0x40 +#define ADCON0_BD 0x80 #endif #ifdef ADCON1 #undef ADCON1 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific // Not directly accessible ADCON1 -#define ADCON1_MX0 0x01 -#define ADCON1_MX1 0x02 -#define ADCON1_MX2 0x04 -#define ADCON1_ADCL 0x80 +#define ADCON1_MX0 0x01 +#define ADCON1_MX1 0x02 +#define ADCON1_MX2 0x04 +#define ADCON1_ADCL 0x80 +#endif + +#ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 +#undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0 +sfr at 0xC5 ADCON ; // A/D control, P80C552 specific +// Not directly accessible Bits. +#define AADR0 0x01 +#define AADR1 0x02 +#define AADR2 0x04 +#define ADCS 0x08 +#define ADCI 0x10 +#define ADEX 0x20 +#define ADC_0 0x40 // different name as ADC0 in P5 +#define ADC_1 0x80 // different name as ADC1 in P5 #endif #ifdef ADDAT @@ -839,6 +1488,29 @@ sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific sfr at 0xEF ARCON ; // arithmetic control register SAB80517 #endif +#ifdef AP +#undef AP +sfr at 0x9C AP ; // DS80C390 +#endif + +#ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0 +#undef AUXR__x__x__x__x__x__x__EXTRAM__A0 +// P89C668 specific, Auxilary +sfr at 0x8E AUXR ; +// not bit addressable: +#define EXTRAM 0x02 +#define A0 0x01 +#endif + +#ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 +#undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 +sfr at 0x8E AUXR; +#define AO 0x01 +#define EXTRAM 0x02 +#define XRS0 0x04 +#define XRS1 0x08 +#define M0 0x20 +#endif #ifdef B #undef B sfr at 0xF0 B ; @@ -853,11 +1525,451 @@ sbit at 0xF6 BREG_F6 ; sbit at 0xF7 BREG_F7 ; #endif +#ifdef AUXR1__x__x__x__x__GF3__x__x__DPS +#undef AUXR1__x__x__x__x__GF3__x__x__DPS +sfr at 0xA2 AUXR1; +#define DPS 0x01 +#define GF3 0x08 +#endif + +#ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +#undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +// P89C668 specific, Auxilary 1 +sfr at 0xA2 AUXR1 ; +#define ENBOOT 0x20 +#define GF2 0x08 +#define ALWAYS_ZERO 0x04 +#define DPS 0x01 +#endif + +#ifdef BP2 +#undef BP2 +sfr at 0xC3 BP2 ; +// Not directly accessible bits +#define MS0 0x01 +#define MS1 0x02 +#define MS2 0x04 +#define LB1 0x08 +#define LB2 0x10 +#define LB3 0x20 +#endif + +#ifdef C0C +#undef C0C +sfr at 0xA3 C0C ; // DS80C390 specific +// Not directly accessible bits +#define SWINT 0x01 +#define ERCS 0x02 +#define AUTOB 0x04 +#define CRST 0x08 +#define SIESTA 0x10 +#define PDE 0x20 +#define STIE 0x40 +#define ERIE 0x80 +#endif + +#ifdef C0IR +#undef C0IR +sfr at 0xA5 C0IR ; // DS80C390 specific +// Not directly accessible bits +#define INTIN0 0x01 +#define INTIN1 0x02 +#define INTIN2 0x04 +#define INTIN3 0x08 +#define INTIN4 0x10 +#define INTIN5 0x20 +#define INTIN6 0x40 +#define INTIN7 0x80 +#endif + +#ifdef C0M1C +#undef C0M1C +sfr at 0xAB C0M1C ; // DS80C390 specific +// Not directly accessible bits +#define DTUP 0x01 +#define ROW_TIH 0x02 +#define MTRQ 0x04 +#define EXTRQ 0x08 +#define INTRQ 0x10 +#define ERI 0x20 +#define ETI 0x40 +#define MSRDY 0x80 +#endif + +#ifdef C0M2C +#undef C0M2C +sfr at 0xAC C0M2C ; // DS80C390 specific +#endif + +#ifdef C0M3C +#undef C0M3C +sfr at 0xAD C0M3C ; // DS80C390 specific +#endif + +#ifdef C0M4C +#undef C0M4C +sfr at 0xAE C0M4C ; // DS80C390 specific +#endif + +#ifdef C0M5C +#undef C0M5C +sfr at 0xAF C0M5C ; // DS80C390 specific +#endif + +#ifdef C0M6C +#undef C0M6C +sfr at 0xB3 C0M6C ; // DS80C390 specific +#endif + +#ifdef C0M7C +#undef C0M7C +sfr at 0xB4 C0M7C ; // DS80C390 specific +#endif + +#ifdef C0M8C +#undef C0M8C +sfr at 0xB5 C0M8C ; // DS80C390 specific +#endif + +#ifdef C0M9C +#undef C0M9C +sfr at 0xB6 C0M9C ; // DS80C390 specific +#endif + +#ifdef C0M10C +#undef C0M10C +sfr at 0xB7 C0M10C ; // DS80C390 specific +#endif + +#ifdef C0M11C +#undef C0M11C +sfr at 0xBB C0M11C ; // DS80C390 specific +#endif + +#ifdef C0M12C +#undef C0M12C +sfr at 0xBC C0M12C ; // DS80C390 specific +#endif + +#ifdef C0M13C +#undef C0M13C +sfr at 0xBD C0M13C ; // DS80C390 specific +#endif + +#ifdef C0M14C +#undef C0M14C +sfr at 0xBE C0M14C ; // DS80C390 specific +#endif + +#ifdef C0M15C +#undef C0M15C +sfr at 0xBF C0M15C ; // DS80C390 specific +#endif + +#ifdef C0RE +#undef C0RE +sfr at 0xA7 C0RE ; // DS80C390 specific +#endif + +#ifdef C0RMS0 +#undef C0RMS0 +sfr at 0x96 C0RMS0 ; // DS80C390 specific +#endif + +#ifdef C0RMS1 +#undef C0RMS1 +sfr at 0x97 C0RMS1 ; // DS80C390 specific +#endif + +#ifdef C0S +#undef C0S +sfr at 0xA4 C0S ; // DS80C390 specific +// Not directly accessible bits +#define ER0 0x01 +#define ER1 0x02 +#define ER2 0x04 +#define TXS 0x08 +#define RXS 0x10 +#define WKS 0x20 +#define EC96_128 0x40 +#define BSS 0x80 +#endif + +#ifdef C0TE +#undef C0TE +sfr at 0xA6 C0TE ; // DS80C390 specific +#endif + +#ifdef C0TMA0 +#undef C0TMA0 +sfr at 0x9E C0TMA0 ; // DS80C390 specific +#endif + +#ifdef C0TMA1 +#undef C0TMA1 +sfr at 0x9F C0TMA1 ; // DS80C390 specific +#endif + +#ifdef C1C +#undef C1C +sfr at 0xE3 C1C ; // DS80C390 specific +// Not directly accessible bits +#define SWINT 0x01 +#define ERCS 0x02 +#define AUTOB 0x04 +#define CRST 0x08 +#define SIESTA 0x10 +#define PDE 0x20 +#define STIE 0x40 +#define ERIE 0x80 +#endif + +#ifdef C1IR +#undef C1IR +sfr at 0xE5 C1IR ; // DS80C390 specific +// Not directly accessible bits +#define INTIN0 0x01 +#define INTIN1 0x02 +#define INTIN2 0x04 +#define INTIN3 0x08 +#define INTIN4 0x10 +#define INTIN5 0x20 +#define INTIN6 0x40 +#define INTIN7 0x80 +#endif + +#ifdef C1IRE +#undef C1IRE +sfr at 0xE7 C1RE ; // DS80C390 specific +#endif + +#ifdef C1M1C +#undef C1M1C +sfr at 0xEB C1M1C ; // DS80C390 specific +#endif + +#ifdef C1M2C +#undef C1M2C +sfr at 0xEC C1M2C ; // DS80C390 specific +#endif + +#ifdef C1M3C +#undef C1M3C +sfr at 0xED C1M3C ; // DS80C390 specific +#endif + +#ifdef C1M4C +#undef C1M4C +sfr at 0xEE C1M4C ; // DS80C390 specific +#endif + +#ifdef C1M5C +#undef C1M5C +sfr at 0xEF C1M5C ; // DS80C390 specific +#endif + +#ifdef C1M6C +#undef C1M6C +sfr at 0xF3 C1M6C ; // DS80C390 specific +#endif + +#ifdef C1M7C +#undef C1M7C +sfr at 0xF4 C1M7C ; // DS80C390 specific +#endif + +#ifdef C1M8C +#undef C1M8C +sfr at 0xF5 C1M8C ; // DS80C390 specific +#endif + +#ifdef C1M9C +#undef C1M9C +sfr at 0xF6 C1M9C ; // DS80C390 specific +#endif + +#ifdef C1M10C +#undef C1M10C +sfr at 0xF7 C1M10C ; // DS80C390 specific +#endif + +#ifdef C1M11C +#undef C1M11C +sfr at 0xFB C1M11C ; // DS80C390 specific +#endif + +#ifdef C1M12C +#undef C1M12C +sfr at 0xFC C1M12C ; // DS80C390 specific +#endif + +#ifdef C1M13C +#undef C1M13C +sfr at 0xFD C1M13C ; // DS80C390 specific +#endif + +#ifdef C1M14C +#undef C1M14C +sfr at 0xFE C1M14C ; // DS80C390 specific +#endif + +#ifdef C1M15C +#undef C1M15C +sfr at 0xFF C1M15C ; // DS80C390 specific +#endif + +#ifdef C1S +#undef C1S +sfr at 0xE4 C1S ; // DS80C390 specific +// Not directly accessible bits +#define ER0 0x01 +#define ER1 0x02 +#define ER2 0x04 +#define TXS 0x08 +#define RXS 0x10 +#define WKS 0x20 +#define CECE 0x40 +#define BSS 0x80 +#endif + +#ifdef C1ITE +#undef C1ITE +sfr at 0xE6 C1TE ; // DS80C390 specific +#endif + +#ifdef C1RSM0 +#undef C1RSM0 +sfr at 0xD6 C1RSM0 ; // DS80C390 specific +#endif + +#ifdef C1RSM1 +#undef C1RSM1 +sfr at 0xD7 C1RSM1 ; // DS80C390 specific +#endif + +#ifdef C1TMA0 +#undef C1TMA0 +sfr at 0xDE C1TMA0 ; // DS80C390 specific +#endif + +#ifdef C1TMA1 +#undef C1TMA1 +sfr at 0xDF C1TMA1 ; // DS80C390 specific +#endif + #ifdef CC4EN #undef CC4EN sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific #endif +#ifdef CCAP0H_AT_0XFA +#undef CCAP0H_AT_0XFA +sfr at 0xFA CCAP0H; +#endif + +#ifdef CCAP1H_AT_0XFB +#undef CCAP1H_AT_0XFB +sfr at 0xFB CCAP1H; +#endif + +#ifdef CCAP2H_AT_0XFC +#undef CCAP2H_AT_0XFC +sfr at 0xFC CCAP2H; +#endif + +#ifdef CCAP3H_AT_0XFD +#undef CCAP3H_AT_0XFD +sfr at 0xFD CCAP3H; +#endif + +#ifdef CCAP4H_AT_0XFE +#undef CCAP4H_AT_0XFE +sfr at 0xFE CCAP4H; +#endif + +#ifdef CCAP0L_AT_0XEA +#undef CCAP0L_AT_0XEA +sfr at 0xEA CCAP0L; +#endif + +#ifdef CCAP1L_AT_0XEB +#undef CCAP1L_AT_0XEB +sfr at 0xEB CCAP1L; +#endif + +#ifdef CCAP2L_AT_0XEC +#undef CCAP2L_AT_0XEC +sfr at 0xEC CCAP2L; +#endif + +#ifdef CCAP3L_AT_0XED +#undef CCAP3L_AT_0XED +sfr at 0xED CCAP3L; +#endif + +#ifdef CCAP4L_AT_0XEE +#undef CCAP4L_AT_0XEE +sfr at 0xEE CCAP4L; +#endif + +#ifdef CCAPM0_AT_0XC2 +#undef CCAPM0_AT_0XC2 +// P89C668 specific, Capture module: +sfr at 0xC2 CCAPM0 ; +#endif + +#ifdef CCAPM0_AT_0XDA +#undef CCAPM0_AT_0XDA +sfr at 0xDA CCAPM0; +#define ECCF 0x01 +#define PWM 0x02 +#define TOG 0x04 +#define MAT 0x08 +#define CAPN 0x10 +#define CAPP 0x20 +#define ECOM 0x40 +#endif + +#ifdef CCAPM1_AT_0XC3 +#undef CCAPM1_AT_0XC3 +sfr at 0xC3 CCAPM1 ; +#endif + +#ifdef CCAPM1_AT_0XDB +#undef CCAPM1_AT_0XDB +sfr at 0xDB CCAPM1; +#endif + +#ifdef CCAPM2_AT_0XC4 +#undef CCAPM2_AT_0XC4 +sfr at 0xC4 CCAPM2 ; +#endif + +#ifdef CCAPM2_AT_0XDC +#undef CCAPM2_AT_0XDC +sfr at 0x0DC CCAPM2; +#endif + +#ifdef CCAPM3_AT_0XC5 +#undef CCAPM3_AT_0XC5 +sfr at 0xC5 CCAPM3 ; +#endif + +#ifdef CCAPM3_AT_0XDD +#undef CCAPM3_AT_0XDD +sfr at 0x0DD CCAPM3; +#endif + +#ifdef CCAPM4_AT_0XDE +#undef CCAPM4_AT_0XDE +sfr at 0x0DE CCAPM4; +#endif + +#ifdef CCAPM4_AT_0XC6 +#undef CCAPM4_AT_0XC6 +sfr at 0xC6 CCAPM4 ; +#endif + #ifdef CCEN #undef CCEN sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific @@ -903,10 +2015,55 @@ sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 speci sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific #endif -#ifdef CKCON -#undef CKCON -sfr at 0x8E CKCON ; // DS80C320 specific -// Not directly accessible Bits. DS80C320 specific +#ifdef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 +#undef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 +sfr at 0xD8 CCON; // T89C51RD2 specific register +// Bit registers +sbit at 0xD8 CCF0; +sbit at 0xD9 CCF1; +sbit at 0xDA CCF2; +sbit at 0xDB CCF3; +sbit at 0xDC CCF4; +sbit at 0xDD CR; +sbit at 0xDE CF; +#endif + +#ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +#undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +// P89C668 specific, PCA Counter control: +sfr at 0xC0 CCON ; +// Bit registers +sbit at 0xC0 CCF0 ; +sbit at 0xC1 CCF1 ; +sbit at 0xC2 CCF2 ; +sbit at 0xC3 CCF3 ; +sbit at 0xC4 CCF4 ; +//sbit at 0xC5 - +sbit at 0xC6 CR ; +sbit at 0xC7 CF ; +#endif + +#ifdef CH_AT_0XF9 +#undef CH_AT_0XF9 +sfr at 0xF9 CH; +#endif + +#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +// P89C668 specific, PCA Counter mode: +sfr at 0xC1 CMOD ; +// not bit addressable: +#define CIDL 0x80 +#define WDTE 0x40 +#define CPS1 0x04 +#define CPS0 0x02 +#define ECF 0x01 +#endif + +#ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +#undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 +sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific +// Not directly accessible Bits. #define MD0 0x01 #define MD1 0x02 #define MD2 0x04 @@ -917,6 +2074,32 @@ sfr at 0x8E CKCON ; // DS80C320 specific #define WD1 0x80 #endif +#ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x +#undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x +sfr at 0x8F CKCON; +#define X2 0x01 +#define T0X2 0x02 +#define T1X2 0x04 +#define T2X2 0x08 +#define SiX2 0x10 +#define PcaX2 0x20 +#define WdX2 0x40 +#endif + +#ifdef CKMOD +#undef CKMOD +sfr at 0x96 CKMOD ; // DS89C420 specific +// Not directly accessible Bits. +#define T0MH 0x08 +#define T1MH 0x10 +#define T2MH 0x20 +#endif + +#ifdef CL_AT_0XE9 +#undef CL_AT_0XE9 +sfr at 0xE9 CL; +#endif + #ifdef CMEN #undef CMEN sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific @@ -962,6 +2145,21 @@ sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific #endif +#ifdef CMH0_AT_0XC9 +#undef CMH0_AT_0XC9 +sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific +#endif + +#ifdef CMH1_AT_0XCA +#undef CMH1_AT_0XCA +sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific +#endif + +#ifdef CMH2_AT_0XCB +#undef CMH2_AT_0XCB +sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific +#endif + #ifdef CML0 #undef CML0 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific @@ -1002,26 +2200,139 @@ sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific #endif +#ifdef CML0_AT_0XA9 +#undef CML0_AT_0XA9 +sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific +#endif + +#ifdef CML1_AT_0XAA +#undef CML1_AT_0XAA +sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific +#endif + +#ifdef CML2_AT_0XAB +#undef CML2_AT_0XAB +sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific +#endif + +#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +sfr at 0xD9 CMOD; +#define ECF 0x01 +#define CPS0 0x02 +#define CPS1 0x04 +#define WDTE 0x40 +#define CIDL 0x80 +#endif + #ifdef CMSEL #undef CMSEL sfr at 0xF7 CMSEL ; // compare input select SAB80517 #endif +#ifdef COR +#undef COR +sfr at 0xCE COR ; // Dallas DS80C390 specific +#define CLKOE 0x01 +#define COD0 0x02 +#define COD1 0x04 +#define C0BPR6 0x08 +#define C0BPR7 0x10 +#define C1BPR6 0x20 +#define C1BPR7 0x40 +#define IRDACK 0x80 +#endif + +#ifdef CRC +#undef CRC +sfr at 0xC1 CRC ; // Dallas DS5001 specific +#define CRC_ 0x01 +#define MDM 0x02 +#define RNGE0 0x10 +#define RNGE1 0x20 +#define RNGE2 0x40 +#define RNGE3 0x80 +#endif + #ifdef CRCH #undef CRCH sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific #endif +#ifdef CRCHIGH +#undef CRCHIGH +sfr at 0xC3 CRCHIGH ; // DS5001 specific +#endif + #ifdef CRCL #undef CRCL sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific #endif -#ifdef CTCON -#undef CTCON +#ifdef CRCLOW +#undef CRCLOW +sfr at 0xC2 CRCLOW ; // DS5001 specific +#endif + +#ifdef CTCOM_AT_0XE1 +#undef CTCOM_AT_0XE1 sfr at 0xE1 CTCON ; // com.timer control register SAB80517 #endif +#ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 +#undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0 +sfr at 0xEB CTCON ; // Capture control, P80C552 specific +// Not directly accessible Bits. +#define CTP0 0x01 +#define CTN0 0x02 +#define CTP1 0x04 +#define CTN1 0x08 +#define CTP2 0x10 +#define CTN2 0x20 +#define CTP3 0x40 +#define CTN3 0x80 +#endif + +#ifdef CTH0_AT_0XCC +#undef CTH0_AT_0XCC +sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific +#endif + +#ifdef CTH1_AT_0XCD +#undef CTH1_AT_0XCD +sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific +#endif + +#ifdef CTH2_AT_0XCE +#undef CTH2_AT_0XCE +sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific +#endif + +#ifdef CTH3_AT_0XCF +#undef CTH3_AT_0XCF +sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific +#endif + +#ifdef CTL0_AT_0XAC +#undef CTL0_AT_0XAC +sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific +#endif + +#ifdef CTL1_AT_0XAD +#undef CTL1_AT_0XAD +sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific +#endif + +#ifdef CTL2_AT_0XAE +#undef CTL2_AT_0XAE +sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific +#endif + +#ifdef CTL3_AT_0XAF +#undef CTL3_AT_0XAF +sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific +#endif + #ifdef CTRELH #undef CTRELH sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517 @@ -1032,13 +2343,13 @@ sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517 #endif -#ifdef DAPR_SAB80515 -#undef DAPR_SAB80515 +#ifdef DAPR__SAB80515 +#undef DAPR__SAB80515 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific #endif -#ifdef DAPR_SAB80517 -#undef DAPR_SAB80517 +#ifdef DAPR__SAB80517 +#undef DAPR__SAB80517 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific #endif @@ -1066,11 +2377,32 @@ sfr at 0x84 DPL1 ; // DS80C320 specific sfr at 0x84 DP1L ; // Alternate name for AT89S53 #endif -#ifdef DPS -#undef DPS +#ifdef DPS__x__x__x__x__x__x__x__SEL +#undef DPS__x__x__x__x__x__x__x__SEL +sfr at 0x86 DPS ; +// Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific +#define SEL 0x01 +#endif + +#ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL +#undef DPS__ID1__ID0__TSL__x__x__x__x__SEL sfr at 0x86 DPS ; -// Not directly accessible DPS Bit. DS80C320 specific -#define SEL_ 0x01 +// Not directly accessible DPS Bit. DS89C390 specific +#define SEL 0x01 +#define TSL 0x20 +#define ID0 0x40 +#define ID1 0x80 +#endif + +#ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL +#undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL +sfr at 0x86 DPS ; +// Not directly accessible DPS Bit. DS89C420 specific +#define SEL 0x01 +#define AID 0x10 +#define TSL 0x20 +#define ID0 0x40 +#define ID1 0x80 #endif #ifdef DPSEL @@ -1078,8 +2410,115 @@ sfr at 0x86 DPS ; sfr at 0x92 DPSEL ; // data pointer select register SAB80517 #endif -#ifdef EXIF_DS80C32X -#undef EXIF_DS80C32X +#ifdef DPX +#undef DPX +sfr at 0x93 DPX1 ; // DS80C390 specific +#endif + +#ifdef DPX1 +#undef DPX1 +sfr at 0x95 DPX1 ; // DS80C390 specific +#endif + +#ifdef EECON +#undef EECON +sfr at 0xD2 EECON; +#define EEBUSY 0x01 +#define EEE 0x02 +#define EEPL0 0x10 +#define EEPL1 0x20 +#define EEPL2 0x40 +#define EEPL3 0x80 +#define EEPL 0xF0 +#endif + +#ifdef EETIM +#undef EETIM +sfr at 0xD3 EETIM; +#endif + +#ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 +#undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2 +sfr at 0xE8 EIE ; +// Bit registers DS80C320 specific +sbit at 0xE8 EX2 ; +sbit at 0xE9 EX3 ; +sbit at 0xEA EX4 ; +sbit at 0xEB EX5 ; +sbit at 0xEC EWDI ; +#endif + +#ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 +#undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2 +sfr at 0xE8 EIE ; +// Bit registers DS80C390 specific +sbit at 0xE8 EX2 ; +sbit at 0xE9 EX3 ; +sbit at 0xEA EX4 ; +sbit at 0xEB EX5 ; +sbit at 0xEC EWDI ; +sbit at 0xED C1IE ; +sbit at 0xEE C0IE ; +sbit at 0xEF CANBIE ; +#endif + +#ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 +#undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2 +sfr at 0xF8 EIP ; +// Bit registers DS80C320 specific +sbit at 0xF8 PX2 ; +sbit at 0xF9 PX3 ; +sbit at 0xFA PX4 ; +sbit at 0xFB PX5 ; +sbit at 0xFC PWDI ; +#endif + +#ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 +#undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0 +sfr at 0xF8 EIP ; +// Bit registers DS80C320 specific +sbit at 0xF8 PX2 ; +sbit at 0xF9 PX3 ; +sbit at 0xFA PX4 ; +sbit at 0xFB PX5 ; +sbit at 0xFC PWDI ; +sbit at 0xFD C1IP ; +sbit at 0xFE C0IP ; +sbit at 0xFF CANBIP ; +#endif + +#ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 +#undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2 +sfr at 0xF8 EIP0 ; +// Bit registers DS89C420 specific +sbit at 0xF8 LPX2 ; +sbit at 0xF9 LPX3 ; +sbit at 0xFA LPX4 ; +sbit at 0xFB LPX5 ; +sbit at 0xFC LPWDI ; +#endif + +#ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 +#undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2 +sfr at 0xF1 EIP1 ; +// Not directly accessible Bits DS89C420 specific +#define MPX2 0x01 +#define MPX3 0x02 +#define MPX4 0x04 +#define MPX5 0x08 +#define MPWDI 0x10 +#endif + +#ifdef ESP +#undef ESP +sfr at 0x9B ESP ; +// Not directly accessible Bits DS80C390 specific +#define ESP_0 0x01 +#define ESP_1 0x02 +#endif + +#ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS +#undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS sfr at 0x91 EXIF ; // Not directly accessible EXIF Bits DS80C320 specific #define BGS 0x01 @@ -1091,8 +2530,8 @@ sfr at 0x91 EXIF ; #define IE5 0x80 #endif -#ifdef EXIF_DS8XC520 -#undef EXIF_DS8XC520 +#ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS +#undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS sfr at 0x91 EXIF ; // Not directly accessible EXIF Bits DS87C520 specific #define BGS 0x01 @@ -1105,30 +2544,53 @@ sfr at 0x91 EXIF ; #define IE5 0x80 #endif -#ifdef EIE -#undef EIE -sfr at 0xE8 EIE ; -// Bit registers DS80C320 specific -sbit at 0xE8 EX2 ; -sbit at 0xE9 EX3 ; -sbit at 0xEA EX4 ; -sbit at 0xEB EX5 ; -sbit at 0xEC EWDI ; +#ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS +#undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS +sfr at 0x91 EXIF ; +// Not directly accessible EXIF Bits DS80C390 & DS89C420 specific +#define BGS 0x01 +#define RGSL 0x02 +#define RGMD 0x04 +#define CKRY 0x08 +#define IE2 0x10 +#define IE3 0x20 +#define IE4 0x40 +#define IE5 0x80 #endif -#ifdef EIP -#undef EIP -sfr at 0xE8 EIP ; -// Bit registers DS80C320 specific -sbit at 0xF8 PX2 ; -sbit at 0xF9 PX3 ; -sbit at 0xFA PX4 ; -sbit at 0xFB PX5 ; -sbit at 0xFC PWDI ; +#ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 +#undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0 +sfr at 0xD5 FCNTL ; +// Not directly accessible DS89C420 specific +#define FC0 0x01 +#define FC1 0x02 +#define FC2 0x04 +#define FC3 0x08 +#define FERR 0x40 +#define FBUSY 0x80 +#endif + +#ifdef FCON +#undef FCON +sfr at 0xD1 FCON; +#define FBUSY 0x01 +#define FMOD0 0x02 +#define FMOD1 0x04 +#define FPS 0x08 +#define FPL0 0x10 +#define FPL1 0x20 +#define FPL2 0x40 +#define FPL3 0x80 +#define FPL 0xF0 #endif -#ifdef IE -#undef IE +#ifdef FDATA +#undef FDATA +sfr at 0xD6 FDATA ; +#endif + +#ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0 +#undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0 sfr at 0xA8 IE ; // Bit registers sbit at 0xA8 EX0 ; @@ -1139,24 +2601,118 @@ sbit at 0xAC ES ; sbit at 0xAF EA ; #endif -#ifdef IE_EXT_8052 -#undef IE_EXT_8052 -// Additional bit register for the 8052 and compatible IE +#ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 +#undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0 +sfr at 0xA8 IE ; +// Bit registers +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; +sbit at 0xAC ES ; +sbit at 0xAD ET2 ; // Enable timer2 interrupt +sbit at 0xAF EA ; +#endif // IE + +#ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 +#undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0 +sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific +sfr at 0xA8 IEN0 ; // alternate name +// Bit registers +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; +sbit at 0xAC ES0 ; +sbit at 0xAD ES1 ; +sbit at 0xAE EAD ; +sbit at 0xAF EEA ; +#endif + +#ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 +#undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0 +sfr at 0xA8 IE; +sbit at 0xA8 EX0; +sbit at 0xA9 ET0; +sbit at 0xAA EX1; +sbit at 0xAB ET1; +sbit at 0xAC ES; +sbit at 0xAD ET2; +sbit at 0xAE EC; +sbit at 0xAF EA; +#endif + +#ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 +#undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0 +sfr at 0xA8 IE ; +// Bit registers +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; +sbit at 0xAC ES ; +sbit at 0xAC ES0 ; // Alternate name sbit at 0xAD ET2 ; // Enable timer2 interrupt +sbit at 0xAE ES1 ; +sbit at 0xAF EA ; #endif // IE -#ifdef IE_EXT_SAB80515X -#undef IE_EXT_SAB80515X -sfr at 0xA8 IEN0 ; -// Additional bit register for the SAB80515 and compatible IE +#ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 +#undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0 +sfr at 0xA8 IE ; +sfr at 0xA8 IEN0 ; // Alternate name +// Bit registers for the SAB80515 and compatible IE +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; +sbit at 0xAC ES ; +sbit at 0xAC ES0 ; +sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific +sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific +sbit at 0xAF EA ; +sbit at 0xAF EAL ; // EA as called by Infineon / Siemens +#endif + +#ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +#undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +// P89C668 specific +sfr at 0xA8 IEN0 ; +// Bit registers +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; sbit at 0xAC ES0 ; -sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific -sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific -sbit at 0xAF EAL ; // EA as called by Infineon / Siemens +sbit at 0xAD ES1 ; +sbit at 0xAE EC ; +sbit at 0xAF EA ; +#endif + +#ifdef IEN1__x__x__x__x__x__x__x__ET2 +#undef IEN1__x__x__x__x__x__x__x__ET2 +// P89C668 specific bit registers +sfr at 0xE8 IEN1 ; +// Bit registers +sbit at 0xE8 ET2 ; #endif -#ifdef IEN1 -#undef IEN1 +#ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 +#undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 +sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific +// Bit registers +sbit at 0xE8 ECT0 ; +sbit at 0xE9 ECT1 ; +sbit at 0xEA ECT2 ; +sbit at 0xEB ECT3 ; +sbit at 0xEC ECM0 ; +sbit at 0xED ECM1 ; +sbit at 0xEE ECM2 ; +sbit at 0xEF ET2 ; +#endif + +#ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC +#undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific // Bit registers sbit at 0xB8 EADC ; // A/D converter interrupt enable @@ -1169,13 +2725,13 @@ sbit at 0xBE SWDT ; // watchdog timer start/reset sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable #endif -#ifdef IEN2_SAB80517 -#undef IEN2_SAB80517 +#ifdef IEN2__SAB80517 +#undef IEN2__SAB80517 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517 #endif -#ifdef IP -#undef IP +#ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0 +#undef IP__x__x__x__PS__PT1__PX1__PT0__PX0 sfr at 0xB8 IP ; // Bit registers sbit at 0xB8 PX0 ; @@ -1185,23 +2741,90 @@ sbit at 0xBB PT1 ; sbit at 0xBC PS ; #endif -#ifdef IP_EXT_AT89X52_55 -#undef IP_EXT_AT89X52_55 -// Additional bit register for the AT89C52 and compatible -sbit at 0xBD PT2 ; +#ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 +#undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0 +sfr at 0xB8 IP ; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS ; +sbit at 0xBC PS0 ; // alternate name +sbit at 0xBD PT2 ; #endif -#ifdef IP_EXT_DS80C320 -#undef IP_EXT_DS80C320 -// Additional bit register for the DS80C320 and compatible -sbit at 0xBD PT2 ; -sbit at 0xBE PS1 ; +#ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 +#undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0 +sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific +sfr at 0xB8 IP0 ; // alternate name +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS0 ; +sbit at 0xBD PS1 ; +sbit at 0xBE PAD ; +#endif + +#ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 +#undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0 +sfr at 0xB8 IP; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS ; +sbit at 0xBD PT2 ; +sbit at 0xBE PPC ; #endif -#ifdef IP0 -#undef IP0 -sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific -// Not directly accessible IP1 bits +#ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 +#undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0 +sfr at 0xB8 IP ; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS ; +sbit at 0xBD PT2 ; +sbit at 0xBE PS1 ; +#endif + +#ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +#undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +// P89C668 specific: +sfr at 0xB8 IP ; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS0 ; +sbit at 0xBD PS1 ; +sbit at 0xBE PPC ; +sbit at 0xBF PT2 ; +#endif + +#ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 +#undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 +sfr at 0xB8 IP ; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS ; +sbit at 0xBF RWT ; +#endif + +#ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 +#undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0 +sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific +// Not directly accessible IP0 bits #define IP0_0 0x01 #define IP0_1 0x02 #define IP0_2 0x04 @@ -1211,9 +2834,22 @@ sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific #define WDTS 0x40 #endif -#ifdef IP1 -#undef IP1 -sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific +#ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 +#undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0 +sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific +// Not directly accessible IP0 bits +#define LPX0 0x01 +#define LPT0 0x02 +#define LPX1 0x04 +#define LPT1 0x08 +#define LPS0 0x10 +#define LPT2 0x20 +#define LPS1 0x40 +#endif + +#ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 +#undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0 +sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific // Not directly accessible IP1 bits #define IP1_0 0x01 #define IP1_1 0x02 @@ -1223,6 +2859,60 @@ sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific #define IP1_5 0x20 #endif +#ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 +#undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0 +sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific +// Not directly accessible IP0 bits +#define LPX0 0x01 +#define LPT0 0x02 +#define LPX1 0x04 +#define LPT1 0x08 +#define LPS0 0x10 +#define LPT2 0x20 +#define LPS1 0x40 +#endif + +#ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 +#undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0 +sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific +// Bit registers +sbit at 0xF8 PCT0 ; +sbit at 0xF9 PCT1 ; +sbit at 0xFA PCT2 ; +sbit at 0xFB PCT3 ; +sbit at 0xFC PCM0 ; +sbit at 0xFD PCM1 ; +sbit at 0xFE PCM2 ; +sbit at 0xFF PT2 ; +#endif + +#ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H +#undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H +sfr at 0xB7 IPH; +#define PX0H 0x01 +#define PT0H 0x02 +#define PX1H 0x04 +#define PT1H 0x08 +#define PSH 0x10 +#define PT2H 0x20 +#define PPCH 0x40 +#endif + +#ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +#undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +// P89C668 specific: +sfr at 0xB7 IPH ; +// not bit addressable: +#define PX0H 0x01 +#define PT0H 0x02 +#define PX1H 0x04 +#define PT1H 0x08 +#define PS0H 0x10 +#define PS1H 0x20 +#define PPCH 0x40 +#define PT2H 0x80 +#endif + #ifdef IRCON #undef IRCON sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific @@ -1256,6 +2946,80 @@ sbit at 0xC7 EXF2 ; // timer2 reload flag sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific #endif +#ifdef MA +#undef MA +sfr at 0xD3 MA ; // DS80C390 +#endif + +#ifdef MB +#undef MB +sfr at 0xD4 MB ; // DS80C390 +#endif + +#ifdef MC +#undef MC +sfr at 0xD5 MC ; // DS80C390 +#endif + +#ifdef MCNT0 +#undef MCNT0 +sfr at 0xD1 MCNT0 ; // DS80C390 +#define MAS0 0x01 +#define MAS1 0x02 +#define MAS2 0x04 +#define MAS3 0x08 +#define MAS4 0x10 +#define SCB 0x20 +#define CSE 0x40 +#define LSHIFT 0x80 +#endif + +#ifdef MCNT1 +#undef MCNT1 +sfr at 0xD2 MCNT1 ; // DS80C390 +#define CLM 0x10 +#define MOF 0x40 +#define MST 0x80 +#endif + +#ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 +#undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0 +sfr at 0xC6 MCON ; // DS80C390 +#define PDCE0 0x01 +#define PDCE1 0x02 +#define PDCE2 0x04 +#define PDCE3 0x08 +#define CMA 0x20 +#define IDM0 0x40 +#define IDM1 0x80 +#endif + +#ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL +#undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL +sfr at 0xC6 MCON ; // DS5000 +#define SL 0x01 +#define PAA 0x02 +#define ECE2 0x04 +#define RA32_8 0x08 +#define PA0 0x10 +#define PA1 0x20 +#define PA2 0x40 +#define PA3 0x80 +#endif + +#ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL +#undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL +sfr at 0xC6 MCON ; // DS5001 +#define SL 0x01 +#define PM 0x02 +#define PES 0x04 +#define RG1 0x08 +#define PA0 0x10 +#define PA1 0x20 +#define PA2 0x40 +#define PA3 0x80 +#endif + #ifdef MD0 #undef MD0 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517 @@ -1286,6 +3050,11 @@ sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517 #endif +#ifdef MXAX +#undef MXAX +sfr at 0xEA MXAX ; // Dallas DS80C390 +#endif + #ifdef P0 #undef P0 sfr at 0x80 P0 ; @@ -1300,6 +3069,19 @@ sbit at 0x86 P0_6 ; sbit at 0x87 P0_7 ; #endif +#ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +#undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +// P89C668 alternate names for bits in P0 +sbit at 0x80 AD0 ; +sbit at 0x81 AD1 ; +sbit at 0x82 AD2 ; +sbit at 0x83 AD3 ; +sbit at 0x84 AD4 ; +sbit at 0x85 AD5 ; +sbit at 0x86 AD6 ; +sbit at 0x87 AD7 ; +#endif + #ifdef P1 #undef P1 sfr at 0x90 P1 ; @@ -1312,16 +3094,13 @@ sbit at 0x94 P1_4 ; sbit at 0x95 P1_5 ; sbit at 0x96 P1_6 ; sbit at 0x97 P1_7 ; -#ifdef T2MOD -// P1 alternate functions -sbit at 0x90 T2 ; -sbit at 0x91 T2EX ; -#endif #endif -#ifdef P1_EXT_DS80C320 -#undef P1_EXT_DS80C320 +#ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 +#undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2 // P1 alternate functions +sbit at 0x90 T2 ; +sbit at 0x91 T2EX ; sbit at 0x92 RXD1 ; sbit at 0x93 TXD1 ; sbit at 0x94 INT2 ; @@ -1330,7 +3109,21 @@ sbit at 0x96 INT4 ; sbit at 0x97 INT5 ; #endif -#ifdef P1_EXT_SAB80515X +#ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +#undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +// P89C669 alternate names for bits at P1 +// P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +sbit at 0x90 T2 ; +sbit at 0x91 T2EX ; +sbit at 0x92 ECI ; +sbit at 0x93 CEX0 ; +sbit at 0x94 CEX1 ; +sbit at 0x95 CEX2 ; +sbit at 0x96 SCL ; +sbit at 0x97 SDA ; +#endif + +#ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific sbit at 0x91 INT4_CC1 ; sbit at 0x92 INT5_CC2 ; @@ -1341,6 +3134,26 @@ sbit at 0x96 CLKOUT ; sbit at 0x97 T2 ; #endif +#ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA +#undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA +// Bit registers +sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific +sbit at 0x91 CT1I ; +sbit at 0x92 CT2I ; +sbit at 0x93 CT3I ; +sbit at 0x94 T2 ; +sbit at 0x95 RT2 ; +sbit at 0x96 SCL ; +sbit at 0x97 SDA ; +#endif + +#ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2 +#undef P1_EXT__x__x__x__x__x__x__T2EX__T2 +// P1 alternate functions +sbit at 0x90 T2 ; +sbit at 0x91 T2EX ; +#endif + #ifdef P2 #undef P2 sfr at 0xA0 P2 ; @@ -1355,6 +3168,19 @@ sbit at 0xA6 P2_6 ; sbit at 0xA7 P2_7 ; #endif +#ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +#undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +// P89C668 specific bit registers at P2: +sbit at 0xA0 AD8 ; +sbit at 0xA1 AD9 ; +sbit at 0xA2 AD10 ; +sbit at 0xA3 AD11 ; +sbit at 0xA4 AD12 ; +sbit at 0xA5 AD13 ; +sbit at 0xA6 AD14 ; +sbit at 0xA7 AD15 ; +#endif + #ifdef P3 #undef P3 sfr at 0xB0 P3 ; @@ -1365,21 +3191,76 @@ sbit at 0xB2 P3_2 ; sbit at 0xB3 P3_3 ; sbit at 0xB4 P3_4 ; sbit at 0xB5 P3_5 ; +#ifndef MCS51REG_EXTERNAL_RAM sbit at 0xB6 P3_6 ; sbit at 0xB7 P3_7 ; +#endif // alternate names sbit at 0xB0 RXD ; +sbit at 0xB0 RXD0 ; sbit at 0xB1 TXD ; +sbit at 0xB1 TXD0 ; sbit at 0xB2 INT0 ; sbit at 0xB3 INT1 ; sbit at 0xB4 T0 ; sbit at 0xB5 T1 ; +#ifndef MCS51REG_EXTERNAL_RAM sbit at 0xB6 WR ; sbit at 0xB7 RD ; #endif +#endif + +#ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x +#undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x +// P89C668 specific bit registers at P3 (alternate names) +sbit at 0xB5 CEX4 ; +sbit at 0xB4 CEX3 ; +#endif -#ifdef P4_SAB80515 -#undef P4_SAB80515 +#ifdef P4_AT_0X80 +#undef P4_AT_0X80 +sfr at 0x80 P4 ; // Port 4 - DS80C390 +// Bit registers +sbit at 0x80 P4_0 ; +sbit at 0x81 P4_1 ; +sbit at 0x82 P4_2 ; +sbit at 0x83 P4_3 ; +sbit at 0x84 P4_4 ; +sbit at 0x85 P4_5 ; +sbit at 0x86 P4_6 ; +sbit at 0x87 P4_7 ; +#endif + +#ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 +#undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0 +sfr at 0xC0 P4 ; // Port 4, P80C552 specific +// Bit registers +sbit at 0xC0 CMSR0 ; +sbit at 0xC1 CMSR1 ; +sbit at 0xC2 CMSR2 ; +sbit at 0xC3 CMSR3 ; +sbit at 0xC4 CMSR4 ; +sbit at 0xC5 CMSR5 ; +sbit at 0xC6 CMT0 ; +sbit at 0xC7 CMT1 ; +#endif + +#ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 +#undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0 +sfr at 0xC0 P4 ; // Port 4, T89C51 specific +// Bit registers +sbit at 0xC0 P4_0 ; +sbit at 0xC1 P4_1 ; +sbit at 0xC2 P4_2 ; +sbit at 0xC3 P4_3 ; +sbit at 0xC4 P4_4 ; +sbit at 0xC5 P4_5 ; +sbit at 0xC6 P4_6 ; +sbit at 0xC7 P4_7 ; +#endif + +#ifdef P4_AT_0XE8 +#undef P4_AT_0XE8 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers // Bit registers sbit at 0xE8 P4_0 ; @@ -1392,8 +3273,68 @@ sbit at 0xEE P4_6 ; sbit at 0xEF P4_7 ; #endif -#ifdef P5_SAB80515 -#undef P5_SAB80515 +#ifdef P4CNT +#undef P4CNT +sfr at 0x92 P4CNT ; // DS80C390 +// Not directly accessible bits +#define P4CNT_0 0x01 +#define P4CNT_1 0x02 +#define P4CNT_2 0x04 +#define P4CNT_3 0x08 +#define P4CNT_4 0x10 +#define P4CNT_5 0x20 +#define SBCAN 0x40 +#endif + +#ifdef P5_AT_0XA1 +#undef P5_AT_0XA1 +sfr at 0xA1 P5 ; // Port 5 - DS80C390 +#endif + +#ifdef P5_AT_0XE8 +#undef P5_AT_0XE8 +sfr at 0xE8 P5; // Port 5 - T89C51RD2 +// Bit registers +sbit at 0xE8 P5_0; +sbit at 0xE9 P5_1; +sbit at 0xEA P5_2; +sbit at 0xEB P5_3; +sbit at 0xEC P5_4; +sbit at 0xED P5_5; +sbit at 0xEE P5_6; +sbit at 0xEF P5_7; +#endif + +#ifdef P5CNT +#undef P5CNT +sfr at 0xA2 P5CNT ; // DS80C390 +// Not directly accessible bits +#define P5CNT_0 0x01 +#define P5CNT_1 0x02 +#define P5CNT_2 0x04 +#define C0_I_O 0x08 +#define C1_I_O 0x10 +#define SP1EC 0x20 +#define SBCAN0BA 0x40 +#define SBCAN1BA 0x80 +#endif + +#ifdef P5_AT_0XC4 +#undef P5_AT_0XC4 +sfr at 0xC4 P5 ; // Port 5, P80C552 specific +// Not directly accessible Bits. +#define ADC0 0x01 +#define ADC1 0x02 +#define ADC2 0x04 +#define ADC3 0x08 +#define ADC4 0x10 +#define ADC5 0x20 +#define ADC6 0x40 +#define ADC7 0x80 +#endif + +#ifdef P5_AT_0XF8 +#undef P5_AT_0XF8 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers // Bit registers sbit at 0xF8 P5_0 ; @@ -1406,28 +3347,35 @@ sbit at 0xFE P5_6 ; sbit at 0xFF P5_7 ; #endif -#ifdef P6_SAB80515 -#undef P6_SAB80515 +#ifdef P6_AT_0XDB +#undef P6_AT_0XDB sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers #endif -#ifdef P6_SAB80517 -#undef P6_SAB80517 +#ifdef P6_AT_0XFA +#undef P6_AT_0XFA sfr at 0xFA P6 ; // Port 6 - SAB80517 specific #endif -#ifdef P7_SAB80517 -#undef P7_SAB80517 +#ifdef P7_AT_0XDB +#undef P7_AT_0XDB sfr at 0xDB P7 ; // Port 7 - SAB80517 specific #endif -#ifdef P8_SAB80517 -#undef P8_SAB80517 +#ifdef P8_AT_0XDD +#undef P8_AT_0XDD sfr at 0xDD P8 ; // Port 6 - SAB80517 specific #endif -#ifdef PCON -#undef PCON +#ifdef PCON__SMOD__x__x__x__x__x__x__x +#undef PCON__SMOD__x__x__x__x__x__x__x +sfr at 0x87 PCON ; +// Not directly accessible PCON bits +#define SMOD 0x80 +#endif + +#ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL +#undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL sfr at 0x87 PCON ; // Not directly accessible PCON bits #define IDL 0x01 @@ -1437,20 +3385,30 @@ sfr at 0x87 PCON ; #define SMOD 0x80 #endif -#ifdef PCON_80515 -#undef PCON_80515 -sfr at 0x87 PCON ; -// Not directly accessible PCON bits -#define SMOD 0x80 +#ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL +#undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL +sfr at 0x87 PCON ; // PCON, P80C552 specific +// Not directly accessible Bits. +#define IDL 0x01 +#define IDLE 0x01 ; same as IDL +#define PD 0x02 +#define GF0 0x04 +#define GF1 0x08 +#define WLE 0x10 +#define SMOD 0x80 #endif -#ifdef PCON_EXT_80515A -#undef PCON_EXT_80515A +#ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL +#undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL +sfr at 0x87 PCON ; // Not directly accessible PCON bits +#define IDL 0x01 #define IDLE 0x01 ; same as IDL +#define PD 0x02 ; #define PDE 0x02 ; same as PD #define IDLS 0x20 #define PDS 0x40 +#define SMOD 0x80 // alternate names #define PCON_IDLE 0x01 #define PCON_PDE 0x02 @@ -1461,14 +3419,64 @@ sfr at 0x87 PCON ; #define PCON_SMOD 0x80 #endif -#ifdef PCON_EXT_DS8XCX2X -#undef PCON_EXT_DS8XCX2X +#ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL +#undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL +sfr at 0x87 PCON ; +// Not directly accessible PCON bits +#define IDL 0x01 +#define IDLE 0x01 ; same as IDL +#define STOP 0x02 ; +#define EWT 0x04 +#define EPFW 0x08 +#define WTR 0x10 +#define PFW 0x20 +#define POR 0x40 +#define SMOD 0x80 +#endif + +#ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE +#undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE +sfr at 0x87 PCON ; +// Not directly accessible PCON bits +#define IDL 0x01 +#define IDLE 0x01 ; same as IDL +#define STOP 0x02 ; +#define GF0 0x04 +#define GF1 0x08 +#define SMOD0 0x40 +#define SMOD 0x80 +#endif + +#ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE +#undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE +sfr at 0x87 PCON ; // Not directly accessible PCON bits -#define SMOD0 0x40 // DS80C320, DS80C323, DS87C520, DS83C520 +#define IDL 0x01 +#define IDLE 0x01 ; same as IDL +#define STOP 0x02 ; +#define GF0 0x04 +#define GF1 0x08 +#define OFDE 0x10 +#define OFDF 0x20 +#define SMOD0 0x40 +#define SMOD 0x80 +#define SMOD_0 0x80 ; same as SMOD #endif -#ifdef PMR -#undef PMR +#ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL +#undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL +sfr at 0x87 PCON; +#define IDL 0x01 +#define PD 0x02 +#define GF0 0x04 +#define GF1 0x08 +#define POF 0x10 +#define SMOD0 0x40 +#define SMOD1 0x80 +#endif + +#ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 +#undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0 sfr at 0xC4 PMR ; // DS87C520, DS83C520 // Not directly accessible bits #define DME0 0x01 @@ -1480,6 +3488,32 @@ sfr at 0xC4 PMR ; // DS87C520, DS83C520 #define CD1 0x80 #endif +#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x +#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x +sfr at 0xC4 PMR ; // DS80C390 +// Not directly accessible bits +#define ALEOFF 0x04 +#define XTOFF 0x08 +#define _4X_2X 0x10 +#define SWB 0x20 +#define CD0 0x40 +#define CD1 0x80 +#endif + +#ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 +#undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0 +sfr at 0xC4 PMR ; // DS89C420 +// Not directly accessible bits +#define DME0 0x01 +#define DME1 0x02 +#define ALEON 0x04 +#define _4X_2X 0x08 +#define CTM 0x10 +#define SWB 0x20 +#define CD0 0x40 +#define CD1 0x80 +#endif + #ifdef PSW #undef PSW sfr at 0xD0 PSW ; @@ -1494,6 +3528,21 @@ sbit at 0xD6 AC ; sbit at 0xD7 CY ; #endif +#ifdef PWM0_AT_0XFC +#undef PWM0_AT_0XFC +sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific +#endif + +#ifdef PWM1_AT_0XFD +#undef PWM1_AT_0XFD +sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific +#endif + +#ifdef PWMP_AT_0XFE +#undef PWMP_AT_0XFE +sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific +#endif + #ifdef RCAP2H #undef RCAP2H sfr at 0xCB RCAP2H ; @@ -1504,13 +3553,68 @@ sfr at 0xCB RCAP2H ; sfr at 0xCA RCAP2L ; #endif -#ifdef ROMSIZE -#undef ROMSIZE +#ifdef RNR +#undef RNR +sfr at 0xCF RNR ; +#endif + +#ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 +#undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0 +sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520 +// Not directly accessible bits +#define RSM0 0x01 +#define RSM1 0x02 +#define RSM2 0x04 +#endif + +#ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 +#undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0 +sfr at 0xC2 ROMSIZE ; // DS89C420 +// Not directly accessible bits +#define RSM0 0x01 +#define RSM1 0x02 +#define RSM2 0x04 +#define PRAME 0x08 +#endif + +#ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0 +#undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520 // Not directly accessible bits #define RSM0 0x01 #define RSM1 0x02 #define RSM2 0x04 +#define PRAME 0x08 +#define MOVCX 0x10 +#define TE 0x20 +#define BPF 0x40 +#define HBPF 0x80 +#endif + +#ifdef RPCTL +#undef RPCTL +sfr at 0xD8 RPCTL ; // Dallas DS5001 specific +sbit at 0xD8 RG0 ; +sbit at 0xD9 RPCON ; +sbit at 0xDA DMA ; +sbit at 0xDB IBI ; +sbit at 0xDC AE ; +sbit at 0xDD EXBS ; +sbit at 0xDF RNR_FLAG ; +#endif + +#ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 +#undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40 +sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific +// Not directly accessible Bits. +#define RP40 0x01 +#define RP41 0x02 +#define RP42 0x04 +#define RP43 0x08 +#define RP44 0x10 +#define RP45 0x20 +#define TP46 0x40 +#define TP47 0x80 #endif #ifdef S0BUF @@ -1518,9 +3622,33 @@ sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific #endif -#ifdef S0CON -#undef S0CON -sfr at 0x98 S0CON ; // serial channel 0 control register SAB80517 specific +#ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI +#undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI +sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific +// Bit registers +// Already defined in SCON +//sbit at 0x98 RI0 ; +//sbit at 0x99 TI0 ; +//sbit at 0x9A RB8 ; +//sbit at 0x9B TB8 ; +//sbit at 0x9C REN ; +//sbit at 0x9D SM2 ; +//sbit at 0x9E SM1 ; +//sbit at 0x9F SM0 ; +#endif + +#ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 +#undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0 +// serial channel 0 buffer register SAB80517 specific(same as stock SCON) +sfr at 0x98 S0CON ; +sbit at 0x98 RI0 ; +sbit at 0x99 TI0 ; +sbit at 0x9A RB80 ; +sbit at 0x9B TB80 ; +sbit at 0x9C REN0 ; +sbit at 0x9D SM20 ; +sbit at 0x9E SM1 ; +sbit at 0x9F SM0 ; #endif #ifdef S0RELL @@ -1533,16 +3661,50 @@ sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 speci sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific #endif +#ifdef S1ADR__x__x__x__x__x__x__x__GC +#undef S1ADR__x__x__x__x__x__x__x__GC +sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific +// Not directly accessible Bits. +#define GC 0x01 +#endif + #ifdef S1BUF #undef S1BUF sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific #endif -#ifdef S1CON -#undef S1CON +#ifdef S1CON_AT_0X9B +#undef S1CON_AT_0X9B sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific #endif +#ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 +#undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 +sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific +sfr at 0xD8 SICON ; // sometimes called SICON +// Bit register +sbit at 0xD8 CR0 ; +sbit at 0xD9 CR1 ; +sbit at 0xDA AA ; +sbit at 0xDB SI ; +sbit at 0xDC ST0 ; +sbit at 0xDD STA ; +sbit at 0xDE ENS1 ; +sbit at 0xDF CR2 ; +#endif + +#ifdef S1DAT_AT_0XDA +#undef S1DAT_AT_0XDA +sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific +sfr at 0xDA SIDAT ; // sometimes called SIDAT +#endif + +#ifdef S1IST_AT_0XDC +#undef S1IST_AT_0XDC +// P89C668 specific +sfr at 0xDC S1IST ; +#endif + #ifdef S1RELL #undef S1RELL sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific @@ -1553,6 +3715,22 @@ sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 speci sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific #endif +#ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x +#undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x +sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific +// Not directly accessible Bits. +#define SC0 0x08 +#define SC1 0x10 +#define SC2 0x20 +#define SC3 0x40 +#define SC4 0x80 +#endif + +#ifdef SADR_AT_0XA9 +#undef SADR_AT_0XA9 +sfr at 0xA9 SADDR ; +#endif + #ifdef SADDR0 #undef SADDR0 // DS80C320 specific @@ -1565,26 +3743,32 @@ sfr at 0xA9 SADDR0 ; sfr at 0xAA SADDR1 ; #endif +#ifdef SADEN_AT_0XB9 +#undef SADEN_AT_0XB9 +sfr at 0xB9 SADEN ; +#endif + #ifdef SADEN0 #undef SADEN0 -// DS80C320 specific +// DS80C320 & DS80C390 specific sfr at 0xB9 SADEN0 ; #endif #ifdef SADEN1 #undef SADEN1 -// DS80C320 specific +// DS80C320 & DS80C390 specific sfr at 0xBA SADEN1 ; #endif #ifdef SBUF #undef SBUF sfr at 0x99 SBUF ; +sfr at 0x99 SBUF0 ; #endif #ifdef SBUF1 #undef SBUF1 -// DS80C320 specific +// DS80C320 & DS80C390 specific sfr at 0xC1 SBUF1 ; #endif @@ -1602,21 +3786,37 @@ sbit at 0x9E SM1 ; sbit at 0x9F SM0 ; #endif +#ifdef SCON0 +#undef SCON0 +sfr at 0x98 SCON0 ; +// Bit registers +sbit at 0x98 RI_0 ; +sbit at 0x99 TI_0 ; +sbit at 0x9A RB8_0 ; +sbit at 0x9B TB8_0 ; +sbit at 0x9C REN_0 ; +sbit at 0x9D SM2_0 ; +sbit at 0x9E SM1_0 ; +sbit at 0x9F SM0_0 ; +sbit at 0x9F FE_0 ; +sbit at 0x9F SM0_FE_0 ; +#endif + #ifdef SCON1 #undef SCON1 -// DS80C320 specific +// DS80C320 - 80C390 specific sfr at 0xC0 SCON1 ; // Bit registers -sbit at 0xC8 RI_1 ; -sbit at 0xC9 TI_1 ; -sbit at 0xCA RB8_1 ; -sbit at 0xCB TB8_1 ; -sbit at 0xCC REN_1 ; -sbit at 0xCD SM2_1 ; -sbit at 0xCE SM1_1 ; -sbit at 0xCF SM0_1 ; -sbit at 0xCF FE_1 ; -sbit at 0xCF SM0_FE_1 ; +sbit at 0xC0 RI_1 ; +sbit at 0xC1 TI_1 ; +sbit at 0xC2 RB8_1 ; +sbit at 0xC3 TB8_1 ; +sbit at 0xC4 REN_1 ; +sbit at 0xC5 SM2_1 ; +sbit at 0xC6 SM1_1 ; +sbit at 0xC7 SM0_1 ; +sbit at 0xC7 FE_1 ; +sbit at 0xC7 SM0_FE_1 ; #endif #ifdef SP @@ -1670,8 +3870,8 @@ sfr at 0xBA SRELH ; // Baudrate generator reload high sfr at 0xAA SRELL ; // Baudrate generator reload low #endif -#ifdef STATUS_DS80C32X -#undef STATUS_DS80C32X +#ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x +#undef STATUS__PIP__HIP__LIP__x__x__x__x__x // DS80C320 specific sfr at 0xC5 STATUS ; // Not directly accessible Bits. DS80C320 specific @@ -1680,8 +3880,47 @@ sfr at 0xC5 STATUS ; #define PIP 0x80 #endif -#ifdef STATUS_DS8XC520 -#undef STATUS_DS8XC520 +#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 +#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 +sfr at 0xC5 STATUS ; // DS80C390 specific +// Not directly accessible Bits. +#define SPRA0 0x01 +#define SPTA0 0x02 +#define SPRA1 0x04 +#define SPTA1 0x08 +#define LIP 0x20 +#define HIP 0x40 +#define PIP 0x80 +#endif + +#ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 +#undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0 +sfr at 0xC5 STATUS ; // DS89C420 specific +// Not directly accessible Bits. +#define SPRA0 0x01 +#define SPTA0 0x02 +#define SPRA1 0x04 +#define SPTA1 0x08 +#define PIS0 0x20 +#define PIS1 0x40 +#define PIS2 0x80 +#endif + +#ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 +#undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0 +sfr at 0xC5 STATUS ; // DS80C390 specific +// Not directly accessible Bits. +#define SPRA0 0x01 +#define SPTA0 0x02 +#define SPRA1 0x04 +#define SPTA1 0x08 +#define LIP 0x20 +#define HIP 0x40 +#define PIP 0x80 +#endif + +#ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 +#undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific // Not directly accessible Bits. #define SPRA0 0x01 @@ -1694,29 +3933,57 @@ sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific #define PIP 0x80 #endif +#ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF +#undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF +sfr at 0xDA STATUS ; // DS5001specific +// Not directly accessible Bits. +#define OBF 0x01 +#define IBF 0x02 +#define F0 0x04 +#define IA0 0x08 +#define ST4 0x10 +#define ST5 0x20 +#define ST6 0x40 +#define ST7 0x80 +#endif + +#ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 +#undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40 +sfr at 0xEE STE ; // Set enable, P80C552 specific +// Not directly accessible Bits. +#define SP40 0x01 +#define SP41 0x02 +#define SP42 0x04 +#define SP43 0x08 +#define SP44 0x10 +#define SP45 0x20 +#define TG46 0x40 +#define TG47 0x80 +#endif + #ifdef SYSCON #undef SYSCON sfr at 0xB1 SYSCON ; // XRAM Controller Access Control // SYSCON bits -#define SYSCON_XMAP0 0x01 -#define SYSCON_XMAP1 0x02 -#define SYSCON_RMAP 0x10 -#define SYSCON_EALE 0x20 +#define SYSCON_XMAP0 0x01 +#define SYSCON_XMAP1 0x02 +#define SYSCON_RMAP 0x10 +#define SYSCON_EALE 0x20 #endif -#ifdef T2CON -#undef T2CON +#ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 sfr at 0xC8 T2CON ; // Definitions for the 8052 compatible microcontrollers. // Bit registers -sbit at 0xC8 CP_RL2 ; -sbit at 0xC9 C_T2 ; -sbit at 0xCA TR2 ; -sbit at 0xCB EXEN2 ; -sbit at 0xCC TCLK ; -sbit at 0xCD RCLK ; -sbit at 0xCE EXF2 ; -sbit at 0xCF TF2 ; +sbit at 0xC8 CP_RL2 ; +sbit at 0xC9 C_T2 ; +sbit at 0xCA TR2 ; +sbit at 0xCB EXEN2 ; +sbit at 0xCC TCLK ; +sbit at 0xCD RCLK ; +sbit at 0xCE EXF2 ; +sbit at 0xCF TF2 ; // alternate names sbit at 0xC8 T2CON_0 ; sbit at 0xC9 T2CON_1 ; @@ -1728,24 +3995,17 @@ sbit at 0xCE T2CON_6 ; sbit at 0xCF T2CON_7 ; #endif -#ifdef T2CON_SABX -#undef T2CON_SABX +#ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 +#undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0 sfr at 0xC8 T2CON ; -// Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517, SAB-C505 compatible -// Microcontrollers. -// Attention! -// SAB-C505 has no I2FR -// SAB-C504 has a 8052 style T2CON -// SAB-C541 has no T2CON +// Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517 // Bit registers sbit at 0xC8 T2I0 ; sbit at 0xC9 T2I1 ; sbit at 0xCA T2CM ; sbit at 0xCB T2R0 ; sbit at 0xCC T2R1 ; -#ifndef MICROCONTROLLER_SABC505 sbit at 0xCD I2FR ; -#endif sbit at 0xCE I3FR ; sbit at 0xCF T2PS ; // alternate names @@ -1759,8 +4019,19 @@ sbit at 0xCE T2CON_6 ; sbit at 0xCF T2CON_7 ; #endif -#ifdef T2MOD -#undef T2MOD +#ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN +#undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN +// Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers +sfr at 0xC9 T2MOD ; +// Not not directly accessible T2MOD bits +#define DCEN 0x01 +#define T2OE 0x02 +#define D13T2 0x08 +#define D13T1 0x10 +#endif + +#ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN +#undef T2MOD__x__x__x__x__x__x__T2OE__DCEN // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller sfr at 0xC9 T2MOD ; // Not not directly accessible T2MOD bits @@ -1771,9 +4042,14 @@ sfr at 0xC9 T2MOD ; #define T2OE_ 0x02 #endif +#ifdef T3_AT_0XFF +#undef T3_AT_0XFF +sfr at 0xFF T3 ; // Timer 3, P80C552 specific +#endif + #ifdef TA #undef TA -// DS80C320 specific +// DS500x, DS80C320 & DS80C390 specific sfr at 0xC7 TA ; #endif @@ -1838,6 +4114,44 @@ sfr at 0x89 TMOD ; #define T1_MASK 0xF0 #endif +#ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 +#undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0 +sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific +// Not directly accessible Bits. +#define T2MS0 0x01 +#define T2MS1 0x02 +#define T2P0 0x04 +#define T2P1 0x08 +#define T2B0 0x10 +#define T2ER 0x20 +#define T2IS0 0x40 +#define T2IS1 0x80 +#endif + +#ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 +#undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0 +sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific +// Bit register +sbit at 0xC8 CTI0 ; +sbit at 0xC9 CTI1 ; +sbit at 0xCA CTI2 ; +sbit at 0xCB CTI3 ; +sbit at 0xCC CMI0 ; +sbit at 0xCD CMI1 ; +sbit at 0xCE CMI2 ; +sbit at 0xCF T20V ; +#endif + +#ifdef TMH2_AT_0XED +#undef TMH2_AT_0XED +sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific +#endif + +#ifdef TML2_AT_0XEC +#undef TML2_AT_0XEC +sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific +#endif + #ifdef WCON #undef WCON sfr at 0x96 WCON ; // AT89S53 specific @@ -1852,17 +4166,25 @@ sfr at 0x96 WCON ; // AT89S53 specific #ifdef WDCON #undef WDCON -// DS80C320 specific +// DS80C320 - 390, DS89C420, etc. specific sfr at 0xD8 WDCON ; -// Not directly accessible bits -#define RWT 0x01 /* Timed-Access protected */ -#define EWT 0x02 /* Timed-Access protected */ -#define WTRF 0x04 -#define WDIF 0x08 /* Timed-Access protected */ -#define PFI 0x10 -#define EPFI 0x20 -#define POR 0x40 /* Timed-Access protected */ -#define SMOD_1 0x80 +// Bit registers +sbit at 0xD8 RWT ; +sbit at 0xD9 EWT ; +sbit at 0xDA WTRF ; +sbit at 0xDB WDIF ; +sbit at 0xDC PFI ; +sbit at 0xDD EPFI ; +sbit at 0xDE POR ; +sbit at 0xDF SMOD_1 ; +#endif + +#ifdef WDTPRG_AT_0XA7 +#undef WDTPRG_AT_0XA7 +sfr at 0xA7 WDTPRG; +#define WDTRPRG_S0 0x01 +#define WDTRPRG_S1 0x02 +#define WDTRPRG_S2 0x04 #endif #ifdef WDTREL @@ -1870,12 +4192,16 @@ sfr at 0xD8 WDCON ; sfr at 0x86 WDTREL ; // Watchdof Timer reload register #endif +#ifdef WDTRST_AT_0XA6 +#undef WDTRST_AT_0XA6 +sfr at 0xA6 WDTRST; +#endif + #ifdef XPAGE #undef XPAGE sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific #endif - ///////////////////////// /// Interrupt vectors /// ///////////////////////// @@ -1887,15 +4213,73 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #define TF1_VECTOR 3 // 0x1b timer 1 #define SI0_VECTOR 4 // 0x23 serial port 0 +#ifdef MICROCONTROLLER_AT89S53 +#define TF2_VECTOR 5 /* 0x2B timer 2 */ +#define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ +#endif + #ifdef MICROCONTROLLER_AT89X52 #define TF2_VECTOR 5 /* 0x2B timer 2 */ #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ #endif +#ifdef MICROCONTROLLER_AT89X55 +#define TF2_VECTOR 5 /* 0x2B timer 2 */ +#define EX2_VECTOR 5 /* 0x2B external interrupt 2 */ +#endif + +#ifdef MICROCONTROLLER_DS5000 +#define PFW_VECTOR 5 /* 0x2B */ +#endif + +#ifdef MICROCONTROLLER_DS5001 +#define PFW_VECTOR 5 /* 0x2B */ +#endif + +#ifdef MICROCONTROLLER_DS80C32X +#define TF2_VECTOR 5 /* 0x2B */ +#define PFI_VECTOR 6 /* 0x33 */ +#define SIO1_VECTOR 7 /* 0x3B */ +#define IE2_VECTOR 8 /* 0x43 */ +#define IE3_VECTOR 9 /* 0x4B */ +#define IE4_VECTOR 10 /* 0x53 */ +#define IE5_VECTOR 11 /* 0x5B */ +#define WDI_VECTOR 12 /* 0x63 */ +#endif + +#ifdef MICROCONTROLLER_DS8XC520 +#define TF2_VECTOR 5 /* 0x2B */ +#define PFI_VECTOR 6 /* 0x33 */ +#define SIO1_VECTOR 7 /* 0x3B */ +#define IE2_VECTOR 8 /* 0x43 */ +#define IE3_VECTOR 9 /* 0x4B */ +#define IE4_VECTOR 10 /* 0x53 */ +#define IE5_VECTOR 11 /* 0x5B */ +#define WDI_VECTOR 12 /* 0x63 */ +#endif + +#ifdef MICROCONTROLLER_P80C552 +#define SIO1_VECTOR 5 // 0x2B SIO1 (I2C) +#define CT0_VECTOR 6 // 0x33 T2 capture 0 +#define CT1_VECTOR 7 // 0x3B T2 capture 1 +#define CT2_VECTOR 8 // 0x43 T2 capture 2 +#define CT3_VECTOR 9 // 0x4B T2 capture 3 +#define ADC_VECTOR 10 // 0x53 ADC completion +#define CM0_VECTOR 11 // 0x5B T2 compare 0 +#define CM1_VECTOR 12 // 0x63 T2 compare 1 +#define CM2_VECTOR 13 // 0x6B T2 compare 2 +#define TF2_VECTOR 14 // 0x73 T2 overflow +#endif + +#ifdef MICROCONTROLLER_P89C668 +#define SIO1_VECTOR 5 // 0x2b SIO1 (i2c) +#define PCA_VECTOR 6 // 0x33 (Programmable Counter Array) +#define TF2_VECTOR 7 // 0x3B (Timer 2) +#endif + #ifdef MICROCONTROLLER_SAB80515 #define TF2_VECTOR 5 // 0x2B timer 2 #define EX2_VECTOR 5 // 0x2B external interrupt 2 - #define IADC_VECTOR 8 // 0x43 A/D converter interrupt #define IEX2_VECTOR 9 // 0x4B external interrupt 2 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 @@ -1907,7 +4291,6 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #ifdef MICROCONTROLLER_SAB80515A #define TF2_VECTOR 5 // 0x2B timer 2 #define EX2_VECTOR 5 // 0x2B external interrupt 2 - #define IADC_VECTOR 8 // 0x43 A/D converter interrupt #define IEX2_VECTOR 9 // 0x4B external interrupt 2 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 @@ -1919,7 +4302,6 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #ifdef MICROCONTROLLER_SAB80517 #define TF2_VECTOR 5 // 0x2B timer 2 #define EX2_VECTOR 5 // 0x2B external interrupt 2 - #define IADC_VECTOR 8 // 0x43 A/D converter interrupt #define IEX2_VECTOR 9 // 0x4B external interrupt 2 #define IEX3_VECTOR 10 // 0x53 external interrupt 3 @@ -1934,4 +4316,13 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #define COMPARE_VECTOR 19 // 0x9B compare #endif -#endif // End of the header -> #ifndef MCS51REG_H \ No newline at end of file +#ifdef MICROCONTORLLER_T89C51RD2 +#define TF2_VECTOR 5 /* 0x2B timer 2 */ +#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */ +#endif /* MICROCONTORLLER_T89C51RD2 */ + +#endif // End of the header -> #ifndef MCS51REG_H + + + +