X-Git-Url: https://git.gag.com/?a=blobdiff_plain;f=Notebook;h=61756e06813aac039de45d7343cc432a25a0f4d7;hb=17d8d7f24585b2384e156b796032f0af2ec97412;hp=1b9250391473d22640746dfb9f57ddbbb809b068;hpb=3a1233682802299fde0d8d0dad4479fdf8e1fc7e;p=hw%2Ftelebt

diff --git a/Notebook b/Notebook
index 1b92503..61756e0 100644
--- a/Notebook
+++ b/Notebook
@@ -71,3 +71,64 @@
   that necessary, such that tightening the SMA nut deflects the wall inward.
   So, 50 mils might indeed be a good choice for TeleBT.  We'll give it a try!
 
+2011.06.07
+- as I start to work on rotating the design, noting the changes between the
+  max 1551 board outline and what I used for v0.1:
+
+  outline layer:
+
+	-       Line[278543 24606 291339 24606 1000 2000 "lock"]
+	-      	Line[291339 24606 291339 129921 1000 2000 "lock"]
+	-      	Line[287402 133854 24606 133854 1000 2000 "lock"]
+	-       Arc[287402 129921 3937 3937 1000 2000 90 90 "lock"]
+	+       Line[278543 24606 286338 24606 1000 2000 "lock"]
+	+       Line[286338 133854 24606 133854 1000 2000 "lock"]
+	+       Line[286338 24606 286338 133854 1000 2000 "lock"]
+
+  similar changes on the top layer:
+
+	-	Line[287402 133854 24606 133854 100 2000 "clearline,lock"]
+	-	Line[24606 133854 24606 121063 100 2000 "clearline,lock"]
+	-	Line[12795 109252 0 109252 100 2000 "clearline,lock"]
+	-	Line[3927 0 266732 0 100 2000 "clearline,lock"]
+	-	Line[291339 24606 291339 129921 100 2000 "clearline,lock"]
+	-	Line[278543 24606 291339 24606 100 2000 "clearline,lock"]
+	-	Line[266732 0 266732 12795 100 2000 "clearline,lock"]
+	-	Line[0 109252 0 3937 100 2000 "clearline,lock"]
+	-	Arc[3937 3937 3937 3937 100 2000 270 90 "clearline,lock"]
+	-	Arc[278543 12795 11811 11811 100 2000 0 90 "clearline,lock"]
+	-	Arc[287402 129921 3937 3937 100 2000 90 90 "clearline,lock"]
+	-	Arc[12795 121063 11811 11811 100 2000 180 90 "clearline,lock"]
+	+	Line[286338 24606 286338 133854 600 2000 "clearline,lock"]
+	+	Line[286338 133854 24606 133854 600 2000 "clearline,lock"]
+	+	Line[24606 133854 24606 121063 600 2000 "clearline,lock"]
+	+	Line[12795 109252 0 109252 600 2000 "clearline,lock"]
+	+	Line[3927 0 266732 0 600 2000 "clearline,lock"]
+	+	Line[278543 24606 286338 24606 600 2000 "clearline,lock"]
+	+	Line[266732 0 266732 12795 600 2000 "clearline,lock"]
+	+	Line[0 109252 0 3937 600 2000 "clearline,lock"]
+	+	Arc[3937 3937 3937 3937 600 2000 270 90 "clearline,lock"]
+	+	Arc[278543 12795 11811 11811 600 2000 0 90 "clearline,lock"]
+	+	Arc[12795 121063 11811 11811 600 2000 180 90 "clearline,lock"]
+
+2013.01.25
+- reviewing design with an eye towards moving to production
+
+	- we have the ability to sample v_lipo, but is it useful?
+
+- need to move design to current preferred parts list
+- verify button fits cleanly through box wall
+- artwork is solid .. did a lot for v0.3
+
+2013.04.08
+- problems in v1.0 build fixed for v1.1
+	+ companion and debug connectors should be rotated so cable dresses
+	  towards center of board like TD
+	+ update D1 footprint to clearly indicate cathode end so we don't
+	  mess that up again
+	+ we're not loading the flash part, so just remove it
+
+2016.03.20
+- to build a TeleBT with BTle:
+	+ swap out Rayson module for DK BM70BLES1FC2-0002AA-ND 
+	? swap out CPU for STM32F042, since it has in-built USB bootloader