X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=tcl%2Fboard%2Fimx27ads.cfg;h=79d3c51359e387c9903ed5fc91d2894037a7092c;hb=4157732bd84c4e9e4b55357e1dc9a96078a35ee1;hp=dc0de4a65f96327a4ff5fe25b9f4b0a91db18c36;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf;p=fw%2Fopenocd

diff --git a/tcl/board/imx27ads.cfg b/tcl/board/imx27ads.cfg
index dc0de4a65..79d3c5135 100644
--- a/tcl/board/imx27ads.cfg
+++ b/tcl/board/imx27ads.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # The IMX27 ADS eval board has a single IMX27 chip
 # Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
 source [find target/imx27.cfg]
@@ -5,7 +7,8 @@ $_TARGETNAME configure -event gdb-attach { reset init }
 $_TARGETNAME configure -event reset-init { imx27ads_init }
 
 # The IMX27 ADS board has a NOR flash on CS0
-flash_bank cfi 0xc0000000 0x00200000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
 
 proc imx27ads_init { } {
 	# This setup puts RAM at 0xA0000000
@@ -24,52 +27,52 @@ proc imx27ads_init { } {
 	# ========================================
 	#  Configure DDR on CSD0 -- initial reset
 	# ========================================
-	mww 0xD8001010 0x00000008 
+	mww 0xD8001010 0x00000008
 
 	# ========================================
-	#  Configure PSRAM on CS5 
+	#  Configure PSRAM on CS5
 	# ========================================
 	mww 0xd8002050 0x0000dcf6
-	mww 0xd8002054 0x444a4541 
-	mww 0xd8002058 0x44443302 
+	mww 0xd8002054 0x444a4541
+	mww 0xd8002058 0x44443302
 
 	#  ========================================
 	#         Configure16 bit NorFlash on CS0
 	#  ========================================
-	mww 0xd8002000 0x0000CC03 
-	mww 0xd8002004 0xa0330D01 
-	mww 0xd8002008 0x00220800 
+	mww 0xd8002000 0x0000CC03
+	mww 0xd8002004 0xa0330D01
+	mww 0xd8002008 0x00220800
 
 	# ========================================
-	#  Configure CPLD on CS4 
+	#  Configure CPLD on CS4
 	# ========================================
-	mww 0xd8002040 0x0000DCF6 
-	mww 0xd8002044 0x444A4541 
-	mww 0xd8002048 0x44443302 
+	mww 0xd8002040 0x0000DCF6
+	mww 0xd8002044 0x444A4541
+	mww 0xd8002048 0x44443302
 
 	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
+	#  Configure DDR on CSD0 -- wait 5000 cycle
 	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
 
-	mww 0xD8001010 0x00000004 
+	mww 0xD8001010 0x00000004
 
-	mww 0xD8001004 0x00795729 
+	mww 0xD8001004 0x00795729
 
-	mww 0xD8001000 0x92200000 
+	mww 0xD8001000 0x92200000
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xA2200000 
+	mww 0xD8001000 0xA2200000
 	mww 0xA0000F00 0x0
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xB2200000 
+	mww 0xD8001000 0xB2200000
 	mwb 0xA0000033 0xFF
 	mwb 0xA1000000 0xAA
 
-	mww 0xD8001000 0x82228085 
+	mww 0xD8001000 0x82228085
 }