X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farm_simulator.c;h=40ca35671d4ac164cef86bf06d4565aad4073575;hb=06d501a192e36986ba0f81c7ddff9298dd0a389e;hp=4ed0558605e17bd5cc030dc608413012848a1711;hpb=13eac429e1b2b6b9061a58c05dc7e67415d5ad0e;p=fw%2Fopenocd

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 4ed055860..40ca35671 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -32,7 +32,7 @@
 
 u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
 {
-	u32 return_value;
+	u32 return_value = 0;
 	shift_amount &= 0xff;
 	
 	if (shift == 0x0) /* LSL */
@@ -160,7 +160,7 @@ u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifte
 	}
 	else
 	{
-		ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
+		LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
 		return_value = 0xffffffff;
 	}
 	
@@ -253,7 +253,7 @@ int pass_condition(u32 cpsr, u32 opcode)
 				
 	}
 	
-	ERROR("BUG: should never get here");
+	LOG_ERROR("BUG: should never get here");
 	return 0;
 }
 
@@ -444,7 +444,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		else
 		{
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
-			WARNING("no updating of flags yet");
+			LOG_WARNING("no updating of flags yet");
 
 			if (instruction.info.data_proc.Rd == 15)  
 				return ERROR_OK;
@@ -460,13 +460,13 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		}
 		else
 		{
-			WARNING("no updating of flags yet");
+			LOG_WARNING("no updating of flags yet");
 		}
 	}
 	/* load register instructions */
 	else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
 	{
-		u32 load_address, modified_address, load_value;
+		u32 load_address = 0, modified_address = 0, load_value;
 		u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
 		
 		/* adjust Rn in case the PC is being read */
@@ -497,7 +497,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		}
 		else
 		{
-			ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
+			LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
 		}
 		
 		if (instruction.info.load_store.index_mode == 0)