X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farm11.h;h=bce5bd9cd36b00139e2ec55fd6745868eaac2881;hb=ac19fc0da7e9b5542d5bcb9d6a6370efdeb2f1ee;hp=fd14720760cc379257b3f210dcb87e95903cc472;hpb=98eea5680b491a26812214ddfeeafb3f088b94aa;p=fw%2Fopenocd

diff --git a/src/target/arm11.h b/src/target/arm11.h
index fd1472076..bce5bd9cd 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,7 +23,7 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include "armv4_5.h"
+#include <target/arm.h>
 #include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
@@ -38,6 +38,7 @@
 		}				\
 	} while (0)
 
+/* bits from ARMv7 DIDR */
 enum arm11_debug_version
 {
 	ARM11_DEBUG_V6			= 0x01,
@@ -52,9 +53,10 @@ struct arm11_common
 
 	/** Debug module state. */
 	struct arm_dpm dpm;
+	struct arm11_sc7_action *bpwp_actions;
+	unsigned bpwp_n;
 
 	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
-	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
 	size_t	free_brps;		/**< Number of breakpoints allocated */
 
 	uint32_t dscr;			/**< Last retrieved DSCR value. */
@@ -93,34 +95,6 @@ enum arm11_instructions
 	ARM11_BYPASS    = 0x1F,
 };
 
-enum arm11_dscr
-{
-	ARM11_DSCR_CORE_HALTED									= 1 << 0,
-	ARM11_DSCR_CORE_RESTARTED								= 1 << 1,
-
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK					= 0x0F << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT					= 0x00 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT				= 0x01 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT				= 0x02 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION		= 0x03 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ					= 0x04 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH			= 0x05 << 2,
-
-	ARM11_DSCR_STICKY_PRECISE_DATA_ABORT					= 1 << 6,
-	ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT					= 1 << 7,
-	ARM11_DSCR_INTERRUPTS_DISABLE							= 1 << 11,
-	ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE				= 1 << 13,
-	ARM11_DSCR_MODE_SELECT									= 1 << 14,
-	ARM11_DSCR_WDTR_FULL									= 1 << 29,
-	ARM11_DSCR_RDTR_FULL									= 1 << 30,
-};
-
-enum arm11_cpsr
-{
-	ARM11_CPSR_T				= 1 << 5,
-	ARM11_CPSR_J				= 1 << 24,
-};
-
 enum arm11_sc7
 {
 	ARM11_SC7_NULL				= 0,
@@ -132,10 +106,4 @@ enum arm11_sc7
 	ARM11_SC7_WCR0				= 112,
 };
 
-struct arm11_reg_state
-{
-	uint32_t				def_index;
-	struct target *			target;
-};
-
 #endif /* ARM11_H */