X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farc.h;h=bb70a598e100a7b4feea7c35be32145485bf66ac;hb=de99836cf639b63dc357a34c13825669af841f17;hp=55a1ead21f9646a6946b9afa6906a33f47e604c8;hpb=c693508f7717d3e5cf118da38d4a5411c59cef1a;p=fw%2Fopenocd diff --git a/src/target/arc.h b/src/target/arc.h index 55a1ead21..bb70a598e 100644 --- a/src/target/arc.h +++ b/src/target/arc.h @@ -1,11 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. * * Frank Dols * * Mischa Jonker * * Anton Kolesov * * Evgeniy Didin * - * * - * SPDX-License-Identifier: GPL-2.0-or-later * ***************************************************************************/ #ifndef OPENOCD_TARGET_ARC_H @@ -27,7 +27,7 @@ #include "arc_cmd.h" #include "arc_mem.h" -#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */ +#define ARC_COMMON_MAGIC 0xB32EB324U /* just a unique number */ #define AUX_DEBUG_REG 0x5 #define AUX_PC_REG 0x6 @@ -45,15 +45,92 @@ #define AUX_STATUS32_REG_HALT_BIT BIT(0) #define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */ -/* Reserved core registers */ -#define CORE_R61_NUM (61) -#define CORE_R62_NUM (62) +/* ARC register numbers */ +enum { + ARC_R0, + ARC_R1, + ARC_R2, + ARC_R3, + ARC_R4, + ARC_R5, + ARC_R6, + ARC_R7, + ARC_R8, + ARC_R9, + ARC_R10, + ARC_R11, + ARC_R12, + ARC_R13, + ARC_R14, + ARC_R15, + ARC_R16, + ARC_R17, + ARC_R18, + ARC_R19, + ARC_R20, + ARC_R21, + ARC_R22, + ARC_R23, + ARC_R24, + ARC_R25, + ARC_GP = 26, + ARC_FP = 27, + ARC_SP = 28, + ARC_ILINK = 29, + ARC_R30, + ARC_BLINK = 31, + ARC_LP_COUNT = 60, + + /* Reserved registers */ + ARC_R61 = 61, + ARC_R62 = 62, + + ARC_PCL = 63, + ARC_PC = 64, + ARC_LP_START = 65, + ARC_LP_END = 66, + ARC_STATUS32 = 67, +}; #define CORE_REG_MAX_NUMBER (63) /* Limit reg_type/reg_type_field name to 20 symbols */ #define REG_TYPE_MAX_NAME_LENGTH 20 +/* ARC 32bits opcodes */ +#define ARC_SDBBP_32 0x256F003FU /* BRK */ + +/* ARC 16bits opcodes */ +#define ARC_SDBBP_16 0x7FFF /* BRK_S */ + +/* Cache registers */ +#define AUX_IC_IVIC_REG 0X10 +#define IC_IVIC_INVALIDATE 0XFFFFFFFF + +#define AUX_DC_IVDC_REG 0X47 +#define DC_IVDC_INVALIDATE BIT(0) +#define AUX_DC_CTRL_REG 0X48 +#define DC_CTRL_IM BIT(6) + +/* L2 cache registers */ +#define SLC_AUX_CACHE_CTRL 0x903 +#define L2_CTRL_IM BIT(6) +#define L2_CTRL_BS BIT(8) /* Busy flag */ +#define SLC_AUX_CACHE_FLUSH 0x904 +#define L2_FLUSH_FL BIT(0) +#define SLC_AUX_CACHE_INV 0x905 +#define L2_INV_IV BIT(0) + + /* Action Point */ +#define AP_AC_AT_INST_ADDR 0x0 +#define AP_AC_AT_MEMORY_ADDR 0x2 +#define AP_AC_AT_AUXREG_ADDR 0x4 + +#define AP_AC_TT_DISABLE 0x00 +#define AP_AC_TT_WRITE 0x10 +#define AP_AC_TT_READ 0x20 +#define AP_AC_TT_READWRITE 0x30 + struct arc_reg_bitfield { struct reg_data_type_bitfield bitfield; char name[REG_TYPE_MAX_NAME_LENGTH]; @@ -72,8 +149,6 @@ struct arc_reg_data_type { }; }; - - /* Standard GDB register types */ static const struct reg_data_type standard_gdb_types[] = { { .type = REG_TYPE_INT, .id = "int" }, @@ -94,16 +169,44 @@ static const struct reg_data_type standard_gdb_types[] = { { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" }, }; +enum arc_actionpointype { + ARC_AP_BREAKPOINT, + ARC_AP_WATCHPOINT, +}; + +/* Actionpoint related fields */ +struct arc_actionpoint { + int used; + uint32_t bp_value; + uint32_t reg_address; + enum arc_actionpointype type; +}; struct arc_common { - uint32_t common_magic; + unsigned int common_magic; struct arc_jtag jtag_info; struct reg_cache *core_and_aux_cache; struct reg_cache *bcr_cache; - /* Indicate if cach was built (for deinit function) */ + /* Cache control */ + bool has_dcache; + bool has_icache; + bool has_l2cache; + /* If true, then D$ has been already flushed since core has been + * halted. */ + bool dcache_flushed; + /* If true, then L2 has been already flushed since core has been + * halted. */ + bool l2cache_flushed; + /* If true, then caches have been already flushed since core has been + * halted. */ + bool icache_invalidated; + bool dcache_invalidated; + bool l2cache_invalidated; + + /* Indicate if cache was built (for deinit function) */ bool core_aux_cache_built; bool bcr_cache_built; /* Closely Coupled memory(CCM) regions for performance-critical @@ -132,6 +235,11 @@ struct arc_common { unsigned long pc_index_in_cache; /* DEBUG register location in register cache. */ unsigned long debug_index_in_cache; + + /* Actionpoints */ + unsigned int actionpoints_num; + unsigned int actionpoints_num_avail; + struct arc_actionpoint *actionpoints_list; }; /* Borrowed from nds32.h */ @@ -241,4 +349,12 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first, int arc_reg_get_field(struct target *target, const char *reg_name, const char *field_name, uint32_t *value_ptr); +int arc_cache_flush(struct target *target); +int arc_cache_invalidate(struct target *target); + +int arc_add_auxreg_actionpoint(struct target *target, + uint32_t auxreg_addr, uint32_t transaction); +int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr); +int arc_set_actionpoints_num(struct target *target, uint32_t ap_num); + #endif /* OPENOCD_TARGET_ARC_H */