X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farc.h;h=8d44bfa41c973dec571d1af9fca51e9b6923cd48;hb=eca4f964b47d317a0eb4b148f11588cec0e3bf60;hp=af4149f978b7d7853f0ac920df7f84512d97a862;hpb=39d54ee96973d3e54a8722112cb9ca25245d01ad;p=fw%2Fopenocd diff --git a/src/target/arc.h b/src/target/arc.h index af4149f97..8d44bfa41 100644 --- a/src/target/arc.h +++ b/src/target/arc.h @@ -33,22 +33,104 @@ #define AUX_PC_REG 0x6 #define AUX_STATUS32_REG 0xA + #define SET_CORE_FORCE_HALT BIT(1) #define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */ -#define SET_CORE_ENABLE_INTERRUPTS BIT(31) +#define SET_CORE_ENABLE_INTERRUPTS BIT(31) +/* STATUS32[5] or AE bit indicates if the processor is in exception state */ +#define SET_CORE_AE_BIT BIT(5) +/* Single instruction step bit in Debug register */ +#define SET_CORE_SINGLE_INSTR_STEP BIT(11) #define AUX_STATUS32_REG_HALT_BIT BIT(0) #define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */ -/* Reserved core registers */ -#define CORE_R61_NUM (61) -#define CORE_R62_NUM (62) +/* ARC register numbers */ +enum { + ARC_R0, + ARC_R1, + ARC_R2, + ARC_R3, + ARC_R4, + ARC_R5, + ARC_R6, + ARC_R7, + ARC_R8, + ARC_R9, + ARC_R10, + ARC_R11, + ARC_R12, + ARC_R13, + ARC_R14, + ARC_R15, + ARC_R16, + ARC_R17, + ARC_R18, + ARC_R19, + ARC_R20, + ARC_R21, + ARC_R22, + ARC_R23, + ARC_R24, + ARC_R25, + ARC_GP = 26, + ARC_FP = 27, + ARC_SP = 28, + ARC_ILINK = 29, + ARC_R30, + ARC_BLINK = 31, + ARC_LP_COUNT = 60, + + /* Reserved registers */ + ARC_R61 = 61, + ARC_R62 = 62, + + ARC_PCL = 63, + ARC_PC = 64, + ARC_LP_START = 65, + ARC_LP_END = 66, + ARC_STATUS32 = 67, +}; #define CORE_REG_MAX_NUMBER (63) /* Limit reg_type/reg_type_field name to 20 symbols */ #define REG_TYPE_MAX_NAME_LENGTH 20 +/* ARC 32bits opcodes */ +#define ARC_SDBBP_32 0x256F003FU /* BRK */ + +/* ARC 16bits opcodes */ +#define ARC_SDBBP_16 0x7FFF /* BRK_S */ + +/* Cache registers */ +#define AUX_IC_IVIC_REG 0X10 +#define IC_IVIC_INVALIDATE 0XFFFFFFFF + +#define AUX_DC_IVDC_REG 0X47 +#define DC_IVDC_INVALIDATE BIT(0) +#define AUX_DC_CTRL_REG 0X48 +#define DC_CTRL_IM BIT(6) + +/* L2 cache registers */ +#define SLC_AUX_CACHE_CTRL 0x903 +#define L2_CTRL_IM BIT(6) +#define L2_CTRL_BS BIT(8) /* Busy flag */ +#define SLC_AUX_CACHE_FLUSH 0x904 +#define L2_FLUSH_FL BIT(0) +#define SLC_AUX_CACHE_INV 0x905 +#define L2_INV_IV BIT(0) + + /* Action Point */ +#define AP_AC_AT_INST_ADDR 0x0 +#define AP_AC_AT_MEMORY_ADDR 0x2 +#define AP_AC_AT_AUXREG_ADDR 0x4 + +#define AP_AC_TT_DISABLE 0x00 +#define AP_AC_TT_WRITE 0x10 +#define AP_AC_TT_READ 0x20 +#define AP_AC_TT_READWRITE 0x30 + struct arc_reg_bitfield { struct reg_data_type_bitfield bitfield; char name[REG_TYPE_MAX_NAME_LENGTH]; @@ -67,8 +149,6 @@ struct arc_reg_data_type { }; }; - - /* Standard GDB register types */ static const struct reg_data_type standard_gdb_types[] = { { .type = REG_TYPE_INT, .id = "int" }, @@ -89,6 +169,18 @@ static const struct reg_data_type standard_gdb_types[] = { { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" }, }; +enum arc_actionpointype { + ARC_AP_BREAKPOINT, + ARC_AP_WATCHPOINT, +}; + +/* Actionpoint related fields */ +struct arc_actionpoint { + int used; + uint32_t bp_value; + uint32_t reg_address; + enum arc_actionpointype type; +}; struct arc_common { uint32_t common_magic; @@ -98,6 +190,22 @@ struct arc_common { struct reg_cache *core_and_aux_cache; struct reg_cache *bcr_cache; + /* Cache control */ + bool has_dcache; + bool has_icache; + bool has_l2cache; + /* If true, then D$ has been already flushed since core has been + * halted. */ + bool dcache_flushed; + /* If true, then L2 has been already flushed since core has been + * halted. */ + bool l2cache_flushed; + /* If true, then caches have been already flushed since core has been + * halted. */ + bool icache_invalidated; + bool dcache_invalidated; + bool l2cache_invalidated; + /* Indicate if cach was built (for deinit function) */ bool core_aux_cache_built; bool bcr_cache_built; @@ -127,6 +235,11 @@ struct arc_common { unsigned long pc_index_in_cache; /* DEBUG register location in register cache. */ unsigned long debug_index_in_cache; + + /* Actionpoints */ + unsigned int actionpoints_num; + unsigned int actionpoints_num_avail; + struct arc_actionpoint *actionpoints_list; }; /* Borrowed from nds32.h */ @@ -155,6 +268,29 @@ static inline struct arc_common *target_to_arc(struct target *target) return target->arch_info; } +/* ----- Inlined functions ------------------------------------------------- */ + +/** + * Convert data in host endianness to the middle endian. This is required to + * write 4-byte instructions. + */ +static inline void arc_h_u32_to_me(uint8_t *buf, int val) +{ + buf[1] = (uint8_t) (val >> 24); + buf[0] = (uint8_t) (val >> 16); + buf[3] = (uint8_t) (val >> 8); + buf[2] = (uint8_t) (val >> 0); +} + +/** + * Convert data in middle endian to host endian. This is required to read 32-bit + * instruction from little endian ARCs. + */ +static inline uint32_t arc_me_to_h_u32(const uint8_t *buf) +{ + return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24); +} + /* ARC Register description */ struct arc_reg_desc { @@ -213,4 +349,12 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first, int arc_reg_get_field(struct target *target, const char *reg_name, const char *field_name, uint32_t *value_ptr); +int arc_cache_flush(struct target *target); +int arc_cache_invalidate(struct target *target); + +int arc_add_auxreg_actionpoint(struct target *target, + uint32_t auxreg_addr, uint32_t transaction); +int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr); +int arc_set_actionpoints_num(struct target *target, uint32_t ap_num); + #endif /* OPENOCD_TARGET_ARC_H */