X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=src%2Fstm32f1%2Fstm32f1.h;h=9d59ebe53069e71edcf67feedbf880752736214c;hb=96cee909d1392f098c22c0122f12e358a7fe8174;hp=a5b579a0e54c6fbe6cdcad6a01195b1316718b15;hpb=96459ad1231898c743aacf3fbc1afbf92f5579dc;p=fw%2Faltos diff --git a/src/stm32f1/stm32f1.h b/src/stm32f1/stm32f1.h index a5b579a0..9d59ebe5 100644 --- a/src/stm32f1/stm32f1.h +++ b/src/stm32f1/stm32f1.h @@ -1204,6 +1204,297 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { stm_afio.exticr[reg] = (stm_afio.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift; } +struct stm_tim18 { + vuint32_t cr1; + vuint32_t cr2; + vuint32_t smcr; + vuint32_t dier; + + vuint32_t sr; + vuint32_t egr; + vuint32_t ccmr1; + vuint32_t ccmr2; + + vuint32_t ccer; + vuint32_t cnt; + vuint32_t psc; + vuint32_t arr; + + vuint32_t rcr; + vuint32_t ccr1; + vuint32_t ccr2; + vuint32_t ccr3; + + vuint32_t ccr4; + uint32_t bdtr; + vuint32_t dcr; + vuint32_t dmar; +}; + +extern struct stm_tim18 stm_tim1, stm_tim8; + +#define stm_tim1 (*((struct stm_tim18 *) 0x40012c00)) +#define stm_tim8 (*((struct stm_tim18 *) 0x40013400)) + +#define STM_TIM18_CR1_CKD 8 +#define STM_TIM18_CR1_CKD_1 0 +#define STM_TIM18_CR1_CKD_2 1 +#define STM_TIM18_CR1_CKD_4 2 +#define STM_TIM18_CR1_CKD_MASK 3UL +#define STM_TIM18_CR1_ARPE 7 +#define STM_TIM18_CR1_CMS 5 +#define STM_TIM18_CR1_CMS_EDGE 0 +#define STM_TIM18_CR1_CMS_CENTER_1 1 +#define STM_TIM18_CR1_CMS_CENTER_2 2 +#define STM_TIM18_CR1_CMS_CENTER_3 3 +#define STM_TIM18_CR1_CMS_MASK 3UL +#define STM_TIM18_CR1_DIR 4 +#define STM_TIM18_CR1_DIR_UP 0 +#define STM_TIM18_CR1_DIR_DOWN 1 +#define STM_TIM18_CR1_OPM 3 +#define STM_TIM18_CR1_URS 2 +#define STM_TIM18_CR1_UDIS 1 +#define STM_TIM18_CR1_CEN 0 + +#define STM_TIM18_CR2_TI1S 7 +#define STM_TIM18_CR2_MMS 4 +#define STM_TIM18_CR2_MMS_RESET 0 +#define STM_TIM18_CR2_MMS_ENABLE 1 +#define STM_TIM18_CR2_MMS_UPDATE 2 +#define STM_TIM18_CR2_MMS_COMPARE_PULSE 3 +#define STM_TIM18_CR2_MMS_COMPARE_OC1REF 4 +#define STM_TIM18_CR2_MMS_COMPARE_OC2REF 5 +#define STM_TIM18_CR2_MMS_COMPARE_OC3REF 6 +#define STM_TIM18_CR2_MMS_COMPARE_OC4REF 7 +#define STM_TIM18_CR2_MMS_MASK 7UL +#define STM_TIM18_CR2_CCDS 3 + +#define STM_TIM18_SMCR_ETP 15 +#define STM_TIM18_SMCR_ECE 14 +#define STM_TIM18_SMCR_ETPS 12 +#define STM_TIM18_SMCR_ETPS_OFF 0 +#define STM_TIM18_SMCR_ETPS_DIV_2 1 +#define STM_TIM18_SMCR_ETPS_DIV_4 2 +#define STM_TIM18_SMCR_ETPS_DIV_8 3 +#define STM_TIM18_SMCR_ETPS_MASK 3UL +#define STM_TIM18_SMCR_ETF 8 +#define STM_TIM18_SMCR_ETF_NONE 0 +#define STM_TIM18_SMCR_ETF_INT_N_2 1 +#define STM_TIM18_SMCR_ETF_INT_N_4 2 +#define STM_TIM18_SMCR_ETF_INT_N_8 3 +#define STM_TIM18_SMCR_ETF_DTS_2_N_6 4 +#define STM_TIM18_SMCR_ETF_DTS_2_N_8 5 +#define STM_TIM18_SMCR_ETF_DTS_4_N_6 6 +#define STM_TIM18_SMCR_ETF_DTS_4_N_8 7 +#define STM_TIM18_SMCR_ETF_DTS_8_N_6 8 +#define STM_TIM18_SMCR_ETF_DTS_8_N_8 9 +#define STM_TIM18_SMCR_ETF_DTS_16_N_5 10 +#define STM_TIM18_SMCR_ETF_DTS_16_N_6 11 +#define STM_TIM18_SMCR_ETF_DTS_16_N_8 12 +#define STM_TIM18_SMCR_ETF_DTS_32_N_5 13 +#define STM_TIM18_SMCR_ETF_DTS_32_N_6 14 +#define STM_TIM18_SMCR_ETF_DTS_32_N_8 15 +#define STM_TIM18_SMCR_ETF_MASK 15UL +#define STM_TIM18_SMCR_MSM 7 +#define STM_TIM18_SMCR_TS 4 +#define STM_TIM18_SMCR_TS_ITR0 0 +#define STM_TIM18_SMCR_TS_ITR1 1 +#define STM_TIM18_SMCR_TS_ITR2 2 +#define STM_TIM18_SMCR_TS_ITR3 3 +#define STM_TIM18_SMCR_TS_TI1F_ED 4 +#define STM_TIM18_SMCR_TS_TI1FP1 5 +#define STM_TIM18_SMCR_TS_TI2FP2 6 +#define STM_TIM18_SMCR_TS_ETRF 7 +#define STM_TIM18_SMCR_TS_MASK 7UL +#define STM_TIM18_SMCR_SMS 0 +#define STM_TIM18_SMCR_SMS_DISABLE 0 +#define STM_TIM18_SMCR_SMS_ENCODER_MODE_1 1 +#define STM_TIM18_SMCR_SMS_ENCODER_MODE_2 2 +#define STM_TIM18_SMCR_SMS_ENCODER_MODE_3 3 +#define STM_TIM18_SMCR_SMS_RESET_MODE 4 +#define STM_TIM18_SMCR_SMS_GATED_MODE 5 +#define STM_TIM18_SMCR_SMS_TRIGGER_MODE 6 +#define STM_TIM18_SMCR_SMS_EXTERNAL_CLOCK 7 +#define STM_TIM18_SMCR_SMS_MASK 7UL + +#define STM_TIM18_DIER_TDE 14 +#define STM_TIM18_DIER_CC4DE 12 +#define STM_TIM18_DIER_CC3DE 11 +#define STM_TIM18_DIER_CC2DE 10 +#define STM_TIM18_DIER_CC1DE 9 +#define STM_TIM18_DIER_UDE 8 + +#define STM_TIM18_DIER_TIE 6 +#define STM_TIM18_DIER_CC4IE 4 +#define STM_TIM18_DIER_CC3IE 3 +#define STM_TIM18_DIER_CC2IE 2 +#define STM_TIM18_DIER_CC1IE 1 +#define STM_TIM18_DIER_UIE 0 + +#define STM_TIM18_SR_CC4OF 12 +#define STM_TIM18_SR_CC3OF 11 +#define STM_TIM18_SR_CC2OF 10 +#define STM_TIM18_SR_CC1OF 9 +#define STM_TIM18_SR_TIF 6 +#define STM_TIM18_SR_CC4IF 4 +#define STM_TIM18_SR_CC3IF 3 +#define STM_TIM18_SR_CC2IF 2 +#define STM_TIM18_SR_CC1IF 1 +#define STM_TIM18_SR_UIF 0 + +#define STM_TIM18_EGR_TG 6 +#define STM_TIM18_EGR_CC4G 4 +#define STM_TIM18_EGR_CC3G 3 +#define STM_TIM18_EGR_CC2G 2 +#define STM_TIM18_EGR_CC1G 1 +#define STM_TIM18_EGR_UG 0 + +#define STM_TIM18_CCMR1_OC2CE 15 +#define STM_TIM18_CCMR1_OC2M 12 +#define STM_TIM18_CCMR1_OC2M_FROZEN 0 +#define STM_TIM18_CCMR1_OC2M_SET_HIGH_ON_MATCH 1 +#define STM_TIM18_CCMR1_OC2M_SET_LOW_ON_MATCH 2 +#define STM_TIM18_CCMR1_OC2M_TOGGLE 3 +#define STM_TIM18_CCMR1_OC2M_FORCE_LOW 4 +#define STM_TIM18_CCMR1_OC2M_FORCE_HIGH 5 +#define STM_TIM18_CCMR1_OC2M_PWM_MODE_1 6 +#define STM_TIM18_CCMR1_OC2M_PWM_MODE_2 7 +#define STM_TIM18_CCMR1_OC2M_MASK 7UL +#define STM_TIM18_CCMR1_OC2PE 11 +#define STM_TIM18_CCMR1_OC2FE 10 +#define STM_TIM18_CCMR1_CC2S 8 +#define STM_TIM18_CCMR1_CC2S_OUTPUT 0 +#define STM_TIM18_CCMR1_CC2S_INPUT_TI2 1 +#define STM_TIM18_CCMR1_CC2S_INPUT_TI1 2 +#define STM_TIM18_CCMR1_CC2S_INPUT_TRC 3 +#define STM_TIM18_CCMR1_CC2S_MASK 3UL + +#define STM_TIM18_CCMR1_OC1CE 7 +#define STM_TIM18_CCMR1_OC1M 4 +#define STM_TIM18_CCMR1_OC1M_FROZEN 0 +#define STM_TIM18_CCMR1_OC1M_SET_HIGH_ON_MATCH 1 +#define STM_TIM18_CCMR1_OC1M_SET_LOW_ON_MATCH 2 +#define STM_TIM18_CCMR1_OC1M_TOGGLE 3 +#define STM_TIM18_CCMR1_OC1M_FORCE_LOW 4 +#define STM_TIM18_CCMR1_OC1M_FORCE_HIGH 5 +#define STM_TIM18_CCMR1_OC1M_PWM_MODE_1 6 +#define STM_TIM18_CCMR1_OC1M_PWM_MODE_2 7 +#define STM_TIM18_CCMR1_OC1M_MASK 7UL +#define STM_TIM18_CCMR1_OC1PE 3 +#define STM_TIM18_CCMR1_OC1FE 2 +#define STM_TIM18_CCMR1_CC1S 0 +#define STM_TIM18_CCMR1_CC1S_OUTPUT 0 +#define STM_TIM18_CCMR1_CC1S_INPUT_TI1 1 +#define STM_TIM18_CCMR1_CC1S_INPUT_TI2 2 +#define STM_TIM18_CCMR1_CC1S_INPUT_TRC 3 +#define STM_TIM18_CCMR1_CC1S_MASK 3UL + +#define STM_TIM18_CCMR1_IC2F 12 +#define STM_TIM18_CCMR1_IC2F_NONE 0 +#define STM_TIM18_CCMR1_IC2F_CK_INT_N_2 1 +#define STM_TIM18_CCMR1_IC2F_CK_INT_N_4 2 +#define STM_TIM18_CCMR1_IC2F_CK_INT_N_8 3 +#define STM_TIM18_CCMR1_IC2F_DTS_2_N_6 4 +#define STM_TIM18_CCMR1_IC2F_DTS_2_N_8 5 +#define STM_TIM18_CCMR1_IC2F_DTS_4_N_6 6 +#define STM_TIM18_CCMR1_IC2F_DTS_4_N_8 7 +#define STM_TIM18_CCMR1_IC2F_DTS_8_N_6 8 +#define STM_TIM18_CCMR1_IC2F_DTS_8_N_8 9 +#define STM_TIM18_CCMR1_IC2F_DTS_16_N_5 10 +#define STM_TIM18_CCMR1_IC2F_DTS_16_N_6 11 +#define STM_TIM18_CCMR1_IC2F_DTS_16_N_8 12 +#define STM_TIM18_CCMR1_IC2F_DTS_32_N_5 13 +#define STM_TIM18_CCMR1_IC2F_DTS_32_N_6 14 +#define STM_TIM18_CCMR1_IC2F_DTS_32_N_8 15 +#define STM_TIM18_CCMR1_IC2PSC 10 +#define STM_TIM18_CCMR1_IC2PSC_NONE 0 +#define STM_TIM18_CCMR1_IC2PSC_2 1 +#define STM_TIM18_CCMR1_IC2PSC_4 2 +#define STM_TIM18_CCMR1_IC2PSC_8 3 +#define STM_TIM18_CCMR1_IC1F 4 +#define STM_TIM18_CCMR1_IC1F_NONE 0 +#define STM_TIM18_CCMR1_IC1F_CK_INT_N_2 1 +#define STM_TIM18_CCMR1_IC1F_CK_INT_N_4 2 +#define STM_TIM18_CCMR1_IC1F_CK_INT_N_8 3 +#define STM_TIM18_CCMR1_IC1F_DTS_2_N_6 4 +#define STM_TIM18_CCMR1_IC1F_DTS_2_N_8 5 +#define STM_TIM18_CCMR1_IC1F_DTS_4_N_6 6 +#define STM_TIM18_CCMR1_IC1F_DTS_4_N_8 7 +#define STM_TIM18_CCMR1_IC1F_DTS_8_N_6 8 +#define STM_TIM18_CCMR1_IC1F_DTS_8_N_8 9 +#define STM_TIM18_CCMR1_IC1F_DTS_16_N_5 10 +#define STM_TIM18_CCMR1_IC1F_DTS_16_N_6 11 +#define STM_TIM18_CCMR1_IC1F_DTS_16_N_8 12 +#define STM_TIM18_CCMR1_IC1F_DTS_32_N_5 13 +#define STM_TIM18_CCMR1_IC1F_DTS_32_N_6 14 +#define STM_TIM18_CCMR1_IC1F_DTS_32_N_8 15 +#define STM_TIM18_CCMR1_IC1PSC 2 +#define STM_TIM18_CCMR1_IC1PSC_NONE 0 +#define STM_TIM18_CCMR1_IC1PSC_2 1 +#define STM_TIM18_CCMR1_IC1PSC_4 2 +#define STM_TIM18_CCMR1_IC1PSC_8 3 + +#define STM_TIM18_CCMR2_OC4CE 15 +#define STM_TIM18_CCMR2_OC4M 12 +#define STM_TIM18_CCMR2_OC4M_FROZEN 0 +#define STM_TIM18_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 +#define STM_TIM18_CCMR2_OC4M_SET_LOW_ON_MATCH 2 +#define STM_TIM18_CCMR2_OC4M_TOGGLE 3 +#define STM_TIM18_CCMR2_OC4M_FORCE_LOW 4 +#define STM_TIM18_CCMR2_OC4M_FORCE_HIGH 5 +#define STM_TIM18_CCMR2_OC4M_PWM_MODE_1 6 +#define STM_TIM18_CCMR2_OC4M_PWM_MODE_2 7 +#define STM_TIM18_CCMR2_OC4M_MASK 7UL +#define STM_TIM18_CCMR2_OC4PE 11 +#define STM_TIM18_CCMR2_OC4FE 10 +#define STM_TIM18_CCMR2_CC4S 8 +#define STM_TIM18_CCMR2_CC4S_OUTPUT 0 +#define STM_TIM18_CCMR2_CC4S_INPUT_TI4 1 +#define STM_TIM18_CCMR2_CC4S_INPUT_TI3 2 +#define STM_TIM18_CCMR2_CC4S_INPUT_TRC 3 +#define STM_TIM18_CCMR2_CC4S_MASK 3UL + +#define STM_TIM18_CCMR2_OC3CE 7 +#define STM_TIM18_CCMR2_OC3M 4 +#define STM_TIM18_CCMR2_OC3M_FROZEN 0 +#define STM_TIM18_CCMR2_OC3M_SET_HIGH_ON_MATCH 1 +#define STM_TIM18_CCMR2_OC3M_SET_LOW_ON_MATCH 2 +#define STM_TIM18_CCMR2_OC3M_TOGGLE 3 +#define STM_TIM18_CCMR2_OC3M_FORCE_LOW 4 +#define STM_TIM18_CCMR2_OC3M_FORCE_HIGH 5 +#define STM_TIM18_CCMR2_OC3M_PWM_MODE_1 6 +#define STM_TIM18_CCMR2_OC3M_PWM_MODE_2 7 +#define STM_TIM18_CCMR2_OC3M_MASK 7UL +#define STM_TIM18_CCMR2_OC3PE 3 +#define STM_TIM18_CCMR2_OC3FE 2 +#define STM_TIM18_CCMR2_CC3S 0 +#define STM_TIM18_CCMR2_CC3S_OUTPUT 0 +#define STM_TIM18_CCMR2_CC3S_INPUT_TI3 1 +#define STM_TIM18_CCMR2_CC3S_INPUT_TI4 2 +#define STM_TIM18_CCMR2_CC3S_INPUT_TRC 3 +#define STM_TIM18_CCMR2_CC3S_MASK 3UL + +#define STM_TIM18_CCER_CC4NP 15 +#define STM_TIM18_CCER_CC4P 13 +#define STM_TIM18_CCER_CC4P_ACTIVE_HIGH 0 +#define STM_TIM18_CCER_CC4P_ACTIVE_LOW 1 +#define STM_TIM18_CCER_CC4E 12 +#define STM_TIM18_CCER_CC3NP 11 +#define STM_TIM18_CCER_CC3P 9 +#define STM_TIM18_CCER_CC3P_ACTIVE_HIGH 0 +#define STM_TIM18_CCER_CC3P_ACTIVE_LOW 1 +#define STM_TIM18_CCER_CC3E 8 +#define STM_TIM18_CCER_CC2NP 7 +#define STM_TIM18_CCER_CC2P 5 +#define STM_TIM18_CCER_CC2P_ACTIVE_HIGH 0 +#define STM_TIM18_CCER_CC2P_ACTIVE_LOW 1 +#define STM_TIM18_CCER_CC2E 4 +#define STM_TIM18_CCER_CC1NP 3 +#define STM_TIM18_CCER_CC1P 1 +#define STM_TIM18_CCER_CC1P_ACTIVE_HIGH 0 +#define STM_TIM18_CCER_CC1P_ACTIVE_LOW 1 +#define STM_TIM18_CCER_CC1E 0 + struct stm_tim234 { vuint32_t cr1; vuint32_t cr2; @@ -1496,6 +1787,44 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1 #define STM_TIM234_CCER_CC1E 0 +struct stm_tim67 { + vuint32_t cr1; + vuint32_t cr2; + uint32_t _unused_08; + vuint32_t dier; + + vuint32_t sr; + vuint32_t egr; + uint32_t _unused_18; + uint32_t _unused_1c; + + uint32_t _unused_20; + vuint32_t cnt; + vuint32_t psc; + vuint32_t arr; +}; + +extern struct stm_tim67 stm_tim6; + +#define STM_TIM67_CR1_ARPE (7) +#define STM_TIM67_CR1_OPM (3) +#define STM_TIM67_CR1_URS (2) +#define STM_TIM67_CR1_UDIS (1) +#define STM_TIM67_CR1_CEN (0) + +#define STM_TIM67_CR2_MMS (4) +#define STM_TIM67_CR2_MMS_RESET 0 +#define STM_TIM67_CR2_MMS_ENABLE 1 +#define STM_TIM67_CR2_MMS_UPDATE 2 +#define STM_TIM67_CR2_MMS_MASK 7UL + +#define STM_TIM67_DIER_UDE (8) +#define STM_TIM67_DIER_UIE (0) + +#define STM_TIM67_SR_UIF (0) + +#define STM_TIM67_EGR_UG (0) + #define isr_decl(name) void stm_ ## name ## _isr(void) isr_decl(halt);