X-Git-Url: https://git.gag.com/?a=blobdiff_plain;ds=sidebyside;f=gdbserver%2Fgdb-server.c;h=fd40fbfad086c0114021479ce74794e32c731450;hb=d5fd6eda08b657c2e916bb3b185f36c70f43feba;hp=d902eab7ea8658af2cc0f25f199630a8919d2a77;hpb=bddf605006b85ccdf7a3ad2be5bb8bcd9b414609;p=fw%2Fstlink
diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c
index d902eab..fd40fbf 100644
--- a/gdbserver/gdb-server.c
+++ b/gdbserver/gdb-server.c
@@ -173,7 +173,7 @@ int main(int argc, char** argv) {
parse_options(argc, argv, &state);
switch (state.stlink_version) {
case 2:
- sl = stlink_open_usb(state.logging_level, 0);
+ sl = stlink_open_usb(state.logging_level, 0, NULL);
if(sl == NULL) return 1;
break;
case 1:
@@ -325,7 +325,11 @@ static const char* const memory_map_template_F4_HD =
""
" " // code = sram, bootrom or flash; flash is bigger
" " // ccm ram
- " " // sram
+ " " // sram
+ " " // fmc bank 1 (nor/psram/sram)
+ " " // fmc bank 2 & 3 (nand flash)
+ " " // fmc bank 4 (pc card)
+ " " // fmc sdram bank 1 & 2
" " //Sectors 0..3
" 0x4000" //16kB
" "
@@ -341,6 +345,28 @@ static const char* const memory_map_template_F4_HD =
" " // option byte area
"";
+static const char* const memory_map_template_F2 =
+ ""
+ ""
+ ""
+ " " // code = sram, bootrom or flash; flash is bigger
+ " " // sram
+ " " //Sectors 0..3
+ " 0x4000" //16kB
+ " "
+ " " //Sector 4
+ " 0x10000" //64kB
+ " "
+ " " //Sectors 5..
+ " 0x20000" //128kB
+ " "
+ " " // peripheral regs
+ " " // cortex regs
+ " " // bootrom
+ " " // option byte area
+ "";
+
static const char* const memory_map_template =
""
"" // option byte area
"";
+static const char* const memory_map_template_F7 =
+ ""
+ ""
+ ""
+ " " // ITCM ram 16kB
+ " " // ITCM flash
+ " " // sram
+ " " // Sectors 0..3
+ " 0x8000" // 32kB
+ " "
+ " " // Sector 4
+ " 0x20000" // 128kB
+ " "
+ " " // Sectors 5..7
+ " 0x40000" // 128kB
+ " "
+ " " // peripheral regs
+ " " // AHB3 Peripherals
+ " " // cortex regs
+ " " // bootrom
+ " " // option byte area
+ "";
+
char* make_memory_map(stlink_t *sl) {
/* This will be freed in serve() */
char* map = malloc(4096);
map[0] = '\0';
- if(sl->chip_id==STM32_CHIPID_F4) {
+ if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
strcpy(map, memory_map_template_F4);
+ } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
+ strcpy(map, memory_map_template_F7);
} else if(sl->chip_id==STM32_CHIPID_F4_HD) {
strcpy(map, memory_map_template_F4_HD);
+ } else if(sl->chip_id==STM32_CHIPID_F2) {
+ snprintf(map, 4096, memory_map_template_F2,
+ sl->flash_size,
+ sl->sram_size,
+ sl->flash_size - 0x20000,
+ sl->sys_base, sl->sys_size);
} else {
snprintf(map, 4096, memory_map_template,
sl->flash_size,
@@ -484,8 +542,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
return -1;
}
-#define CODE_BREAK_NUM 6
-#define CODE_LIT_NUM 2
+int code_break_num;
+int code_lit_num;
+#define CODE_BREAK_NUM_MAX 15
#define CODE_BREAK_LOW 0x01
#define CODE_BREAK_HIGH 0x02
@@ -494,37 +553,41 @@ struct code_hw_breakpoint {
int type;
};
-struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
+struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
static void init_code_breakpoints(stlink_t *sl) {
memset(sl->q_buf, 0, 4);
stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
- if (((val & 3) != 1) ||
- ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) ||
- (((val >> 8) & 0xf) != CODE_LIT_NUM)){
- ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val,
- ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1);
- }
+ code_break_num = ((val >> 4) & 0xf);
+ code_lit_num = ((val >> 8) & 0xf);
+ ILOG("Found %i hw breakpoint registers\n", code_break_num);
- for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ for(int i = 0; i < code_break_num; i++) {
code_breaks[i].type = 0;
stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
}
}
static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
- stm32_addr_t fpb_addr = addr & ~0x3;
- int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
+ stm32_addr_t fpb_addr;
+ uint32_t mask;
+ int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
if(addr & 1) {
ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
return -1;
}
+ if (sl->chip_id==STM32_CHIPID_F7) {
+ fpb_addr = addr;
+ } else {
+ fpb_addr = addr & ~0x3;
+ }
+
int id = -1;
- for(int i = 0; i < CODE_BREAK_NUM; i++) {
+ for(int i = 0; i < code_break_num; i++) {
if(fpb_addr == code_breaks[i].addr ||
(set && code_breaks[i].type == 0)) {
id = i;
@@ -541,16 +604,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
brk->addr = fpb_addr;
- if(set) brk->type |= type;
- else brk->type &= ~type;
+ if (sl->chip_id==STM32_CHIPID_F7) {
+ if(set) brk->type = type;
+ else brk->type = 0;
+
+ mask = (brk->addr) | 1;
+ } else {
+ if(set) brk->type |= type;
+ else brk->type &= ~type;
+
+ mask = (brk->addr) | 1 | (brk->type << 30);
+ }
if(brk->type == 0) {
DLOG("clearing hw break %d\n", id);
stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
} else {
- uint32_t mask = (brk->addr) | 1 | (brk->type << 30);
-
DLOG("setting hw break %d at %08x (%d)\n",
id, brk->addr, brk->type);
DLOG("reg %08x \n",
@@ -643,12 +713,13 @@ static int flash_go(stlink_t *sl) {
// Some kinds of clock settings do not allow writing to flash.
stlink_reset(sl);
+ stlink_force_debug(sl);
for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
- unsigned length = fb->length;
for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) {
+ unsigned length = fb->length - (page - fb->addr);
//Update FLASH_PAGE
stlink_calculate_pagesize(sl, page);
@@ -769,7 +840,9 @@ int serve(stlink_t *sl, st_state_t *st) {
DLOG("query: %s;%s\n", queryName, params);
if(!strcmp(queryName, "Supported")) {
- if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) {
+ if(sl->chip_id==STM32_CHIPID_F4
+ || sl->chip_id==STM32_CHIPID_F4_HD
+ || sl->chip_id==STM32_CHIPID_F7) {
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
}
else {