// ////////////////////////////////////////////////////////////////////////////////
module u2_core
- #(parameter RAM_SIZE=16384)
+ #(parameter RAM_SIZE=32768)
(// Clocks
input dsp_clk,
input wb_clk,
input cpld_din,
input cpld_clk,
input cpld_detached,
- input cpld_misc,
+ output cpld_misc,
input cpld_init_b,
input por,
output config_success,
output [18:0] RAM_A,
output RAM_CE1n,
output RAM_CENn,
- input RAM_CLK,
+ output RAM_CLK,
output RAM_WEn,
output RAM_OEn,
output RAM_LDn,
wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+ wire serdes_link_up;
+ wire epoch;
+
// ///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
- parameter dw = 32; // Data bus width
- parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space
- parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity.
+ localparam dw = 32; // Data bus width
+ localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space
+ localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity.
wire [dw-1:0] m0_dat_o, m0_dat_i;
wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
- s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o;
- wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr;
- wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel;
- wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack;
- wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb;
- wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc;
- wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err;
- wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty;
- wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we;
+ s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
+ wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
+ wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
+ wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
+ wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
+ wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
+ wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
+ wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
+ wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
.s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
.s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
.s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
- .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
+ .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
+ .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
.s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) );
//////////////////////////////////////////////////////////////////////////////////////////
.ram_loader_done_i(ram_loader_done));
assign config_success = ram_loader_done;
+ reg takeover = 0;
+
+ wire cpld_start_int, cpld_mode_int, cpld_done_int;
+
+ always @(posedge wb_clk)
+ if(ram_loader_done)
+ takeover = 1;
+ assign cpld_misc = ~takeover;
+
+ wire sd_clk, sd_csn, sd_mosi, sd_miso;
+
+ assign sd_miso = cpld_din;
+ assign cpld_start = takeover ? sd_clk : cpld_start_int;
+ assign cpld_mode = takeover ? sd_csn : cpld_mode_int;
+ assign cpld_done = takeover ? sd_mosi : cpld_done_int;
// ///////////////////////////////////////////////////////////////////
// RAM Loader
// CPLD Interface
.cfg_clk_i(cpld_clk),
.cfg_data_i(cpld_din),
- .start_o(cpld_start),
- .mode_o(cpld_mode),
- .done_o(cpld_done),
+ .start_o(cpld_start_int),
+ .mode_o(cpld_mode_int),
+ .done_o(cpld_done_int),
.detached_i(cpld_detached),
// Wishbone Interface
.wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
// Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
// I-port connects directly to processor and ram loader
+ wire flush_icache;
ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
- .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+ .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+ .flush_icache(flush_icache));
assign s0_err = 1'b0;
assign s0_rty = 1'b0;
+ setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(),.changed(flush_icache));
+
// Buffer Pool, slave #1
wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
- .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}),
+ .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
);
.in(set_data),.out(serdes_outs),.changed());
setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(adc_outs),.changed());
- setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(leds),.changed());
setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phy_reset),.changed());
+ // /////////////////////////////////////////////////////////////////////////
+ // LEDS
+ // register 8 determines whether leds are controlled by SW or not
+ // 1 = controlled by HW, 0 = by SW
+ // In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+
+ wire [7:0] led_src, led_sw;
+ wire [7:0] led_hw = {clk_status,serdes_link_up};
+
+ setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(led_sw),.changed());
+ setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(led_src),.changed());
+
+ assign leds = (led_src & led_hw) | (~led_src & led_sw);
+
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
- wire [8:0] irq={{6'b0,uart_tx_int, uart_rx_int},
+ wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
- simple_pic #(.is(9),.dwidth(32)) simple_pic
+ simple_pic #(.is(16),.dwidth(32)) simple_pic
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
.irq(irq) );
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
+ reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
+ always @(negedge dsp_clk) pps_negedge <= pps_in;
+ always @(posedge dsp_clk) pps_posedge <= pps_in;
+ always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
+ always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
+
+ wire pps_o;
time_sync time_sync
(.wb_clk_i(wb_clk),.rst_i(wb_rst),
.cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
.we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
.sys_clk_i(dsp_clk),.master_time_o(master_time),
- .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
- .int_o(pps_int) );
+ .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
+ .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+ .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
assign s12_err = 0;
assign s12_rty = 0;
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
- .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+ .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
.debug(debug_rx_dsp) );
tx_control #(.FIFOSIZE(10)) tx_control
.wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
- .debug0(debug_serdes0), .debug1(debug_serdes1) );
+ .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
// ///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
- extram_interface extram_interface
- (.clk(dsp_clk),.rst(dsp_rst),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error),
- .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop),
- .wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error),
- .wr_ready_i(wr3_ready),.wr_full_i(wr3_full),
- .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
- .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn) );
+ localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes
-
+ wire [15:0] bus2ram, ram2bus;
+ wire [15:0] bridge_adr;
+ wire [1:0] bridge_sel;
+ wire bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+
+ wire [19:0] page;
+ wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+ setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(page),.changed());
+
+ wb_bridge_16_32 bridge
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),
+ .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
+ .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+ .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+ .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+ wb_zbt16_b wb_zbt16_b
+ (.clk(wb_clk),.rst(wb_rst),
+ .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+ .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+ .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+ .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+ .sram_mode(),.sram_zz() );
+
+ assign s14_err = 0; assign s14_rty = 0;
+ assign RAM_CE1n = 0;
+ assign RAM_D[17:16] = 2'bzz;
+
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
-
+
// FIFO Level Debugging
- reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug, serdes_to_dsp_fifo, dsp_to_serdes_fifo;
-
+ reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+
always @(posedge dsp_clk)
serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
- {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+ {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
always @(posedge dsp_clk)
dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
- {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
always @(posedge dsp_clk)
host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
{dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
-
+
always @(posedge dsp_clk)
dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
- {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
always @(posedge dsp_clk)
- eth_mac_debug <= {// {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]},
- // {underrun, overrun, debug_mac0[13:0] },
- {debug_txc[15:0]},
- {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+ eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
+ {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
- wire debug_mux;
- setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(debug_mux),.changed());
-
- //assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
- //assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+ assign debug_clk[0] = 0;
+ assign debug_clk[1] = dsp_clk;
- // Assign various commonly used debug buses.
- /*
- wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
- irq[7:0],
- GMII_RXD,
- GMII_TXD};
+ assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+ assign debug_gpio_0 = eth_mac_debug;
+ assign debug_gpio_1 = 0;
- wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+endmodule // u2_core
+
+// wire debug_mux;
+// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+// .in(set_data),.out(debug_mux),.changed());
+
+//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+
+//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign debug = debug_tx_dsp;
+//assign debug = debug_serdes0;
+
+//assign debug_gpio_0 = 0; //debug_serdes0;
+//assign debug_gpio_1 = 0; //debug_serdes1;
+
+// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+// {8'b0},
+// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
+// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
+
+//assign debug = {dac_a,dac_b};
+
+/*
+ assign debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
+
+/*assign debug = host_to_dsp_fifo;
+ assign debug_gpio_0 = eth_mac_debug;
+ assign debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
wire [31:0] debug_time = {uart_tx_o, 7'b0,
irq[7:0],
*/
- // Choose actual debug buses
- assign debug_clk[0] = wb_clk;
- assign debug_clk[1] = dsp_clk;
-
- //assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
- // {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
-
- //assign debug = debug_tx_dsp;
- //assign debug = debug_serdes0;
-
- assign debug_gpio_0 = 0; //debug_serdes0;
- assign debug_gpio_1 = 0; //debug_serdes1;
-
- assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
- {8'b0},
- {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
- {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
-
- //assign debug = {dac_a,dac_b};
-endmodule // u2_core
projects / debian / gnuradio / blobdiff