Merge branch 'new_eth' of http://gnuradio.org/git/matt into master

[debian/gnuradio] / usrp2 / fpga / opencores / sd_interface / RTL / wishBoneBI.v

diff --git a/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v b/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v
deleted file mode 100644 (file)
index 72daaa4..0000000
--- a/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v
+++ /dev/null
@@ -1,145 +0,0 @@
-//////////////////////////////////////////////////////////////////////\r
-////                                                              ////\r
-//// wishBoneBI.v                                                 ////\r
-////                                                              ////\r
-//// This file is part of the usbhostslave opencores effort.\r
-//// <http://www.opencores.org/cores//>                           ////\r
-////                                                              ////\r
-//// Module Description:                                          ////\r
-//// \r
-////                                                              ////\r
-//// To Do:                                                       ////\r
-//// \r
-////                                                              ////\r
-//// Author(s):                                                   ////\r
-//// - Steve Fielding, sfielding@base2designs.com                 ////\r
-////                                                              ////\r
-//////////////////////////////////////////////////////////////////////\r
-////                                                              ////\r
-//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\r
-////                                                              ////\r
-//// This source file may be used and distributed without         ////\r
-//// restriction provided that this copyright statement is not    ////\r
-//// removed from the file and that any derivative work contains  ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-////                                                              ////\r
-//// This source file is free software; you can redistribute it   ////\r
-//// and/or modify it under the terms of the GNU Lesser General   ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any   ////\r
-//// later version.                                               ////\r
-////                                                              ////\r
-//// This source is distributed in the hope that it will be       ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more  ////\r
-//// details.                                                     ////\r
-////                                                              ////\r
-//// You should have received a copy of the GNU Lesser General    ////\r
-//// Public License along with this source; if not, download it   ////\r
-//// from <http://www.opencores.org/lgpl.shtml>                   ////\r
-////                                                              ////\r
-//////////////////////////////////////////////////////////////////////\r
-//\r
-`include "timescale.v"\r
-`include "spiMaster_defines.v"\r
-\r
- \r
-module wishBoneBI (\r
-  clk, rst,\r
-  address, dataIn, dataOut, writeEn, \r
-  strobe_i,\r
-  ack_o,\r
-  ctrlStsRegSel, \r
-  rxFifoSel, txFifoSel,\r
-  dataFromCtrlStsReg,\r
-  dataFromRxFifo,\r
-  dataFromTxFifo  \r
-  );\r
-input clk;\r
-input rst;\r
-input [7:0] address;\r
-input [7:0] dataIn;\r
-output [7:0] dataOut;\r
-input strobe_i;\r
-output ack_o;\r
-input writeEn;\r
-output ctrlStsRegSel;\r
-output rxFifoSel;\r
-output txFifoSel;\r
-input [7:0] dataFromCtrlStsReg;\r
-input [7:0] dataFromRxFifo;\r
-input [7:0] dataFromTxFifo;\r
-\r
-\r
-wire clk;\r
-wire rst;\r
-wire [7:0] address;\r
-wire [7:0] dataIn;\r
-reg [7:0] dataOut;\r
-wire writeEn;\r
-wire strobe_i;\r
-reg ack_o;\r
-reg ctrlStsRegSel;\r
-reg rxFifoSel;\r
-reg txFifoSel;\r
-wire [7:0] dataFromCtrlStsReg;\r
-wire [7:0] dataFromRxFifo;\r
-wire [7:0] dataFromTxFifo;\r
-\r
-//internal wires and regs\r
-reg ack_delayed;\r
-reg ack_immediate;\r
-\r
-//address decode and data mux\r
-always @(address or\r
-  dataFromCtrlStsReg or\r
-  dataFromRxFifo or\r
-  dataFromTxFifo)\r
-begin\r
-  ctrlStsRegSel <= 1'b0;\r
-  rxFifoSel <= 1'b0;\r
-  txFifoSel <= 1'b0;\r
-  case (address & `ADDRESS_DECODE_MASK)\r
-    `CTRL_STS_REG_BASE : begin\r
-      ctrlStsRegSel <= 1'b1;\r
-      dataOut <= dataFromCtrlStsReg;\r
-    end\r
-    `RX_FIFO_BASE : begin\r
-      rxFifoSel <= 1'b1;\r
-      dataOut <= dataFromRxFifo;\r
-    end\r
-    `TX_FIFO_BASE : begin\r
-      txFifoSel <= 1'b1;\r
-      dataOut <= dataFromTxFifo;\r
-    end\r
-    default: \r
-      dataOut <= 8'h00;\r
-  endcase\r
-end\r
-\r
-//delayed ack\r
-always @(posedge clk) begin\r
-  ack_delayed <= strobe_i;\r
-end\r
-\r
-//immediate ack\r
-always @(strobe_i) begin\r
-  ack_immediate <= strobe_i;\r
-end \r
-\r
-//select between immediate and delayed ack\r
-always @(writeEn or address or ack_delayed or ack_immediate) begin\r
-  if (writeEn == 1'b0 &&\r
-      (address == `RX_FIFO_BASE + `FIFO_DATA_REG ||\r
-       address == `TX_FIFO_BASE + `FIFO_DATA_REG) )\r
-  begin\r
-    ack_o <= ack_delayed;\r
-  end\r
-  else\r
-  begin\r
-    ack_o <= ack_immediate;\r
-  end\r
-end\r
-\r
-endmodule\r