remove unused opencores

[debian/gnuradio] / usrp2 / fpga / opencores / ethernet_tri_mode / rtl / verilog / TECH / xilinx / CLK_SWITCH.v

diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CLK_SWITCH.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CLK_SWITCH.v
deleted file mode 100644 (file)
index 0399b9f..0000000
--- a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/xilinx/CLK_SWITCH.v
+++ /dev/null
@@ -1,77 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  CLK_SWITCH.v                                                  ////
-////                                                              ////
-////  This file is part of the Ethernet IP core project           ////
-////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Jon Gao (gaojon@yahoo.com)                            ////
-////                                                              ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2001 Authors                                   ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-//                                                                    
-// CVS Revision History                                               
-//                                                                    
-// $Log: CLK_SWITCH.v,v $
-// Revision 1.1  2006/10/22 16:12:25  maverickist
-// no message
-//
-// Revision 1.1  2006/06/22 09:01:42  Administrator
-// no message
-//
-// Revision 1.2  2005/12/16 06:44:20  Administrator
-// replaced tab with space.
-// passed 9.6k length frame test.
-//
-// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
-// no message
-// 
-
-
-//////////////////////////////////////////////////////////////////////
-// This file can only used for simulation .
-// You need to replace it with your own element according to technology
-//////////////////////////////////////////////////////////////////////
-module CLK_SWITCH (   
-input       IN_0,
-input       IN_1,
-input       SW  ,
-output      OUT 
-
-);
-
-BUFGMUX U_BUFGMUX (
-.O          (OUT        ),
-.I0         (IN_0       ),
-.I1         (IN_1       ),
-.S          (SW         ));
-
-//assign OUT=SW?IN_1:IN_0;
-
-endmodule
\ No newline at end of file