Fix for fifo overruns on eth rx in full duplex. Now send re-pause long before pause...

[debian/gnuradio] / usrp2 / fpga / eth / rtl / verilog / Reg_int.v

diff --git a/usrp2/fpga/eth/rtl/verilog/Reg_int.v b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
index f1bea23162d44055686e662c1099137d276f75fb..bdf73d8e528385c4beb116913b033bb3f5441b8c 100644 (file)
--- a/usrp2/fpga/eth/rtl/verilog/Reg_int.v
+++ b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
@@ -43,6 +43,7 @@ module Reg_int (
   output            tx_pause_en,\r
   output [15:0]     fc_hwmark,\r
   output [15:0]     fc_lwmark,\r
+  output [15:0]     fc_padtime,\r
                \r
   // RMON host interface\r
   output [5:0]      CPU_rd_addr,\r
@@ -141,6 +142,9 @@ module Reg_int (
   RegCPUData #( 13 ) U_0_037( MIIADDRESS                   , 7'd037, 13'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] );\r
   RegCPUData #( 16 ) U_0_038( MIITX_DATA                   , 7'd038, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
 \r
+   // New FC register\r
+  RegCPUData #( 16 ) U_0_041( fc_padtime                   , 7'd041, 1'h0,     RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );\r
+\r
   // Asserted in first clock of 2-cycle access, negated otherwise\r
   wire Access = ~ACK_O & STB_I & CYC_I;\r
 \r
@@ -231,6 +235,7 @@ module Reg_int (
             7'd38: DAT_O <= MIITX_DATA;\r
             7'd39: DAT_O <= MIIRX_DATA;\r
             7'd40: DAT_O <= MIISTATUS;\r
+            7'd41: DAT_O <= fc_padtime;\r
           endcase\r
       end\r
 \r