+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_tx_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_tx_Ctrl.v,v $\r
-// Revision 1.4 2006/06/25 04:58:56 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:54 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.3 2005/12/16 06:44:17 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:38 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_tx_ctrl ( \r
-Reset ,\r
-Clk ,\r
-//CRC_gen Interface \r
-CRC_init ,\r
-Frame_data ,\r
-Data_en ,\r
-CRC_rd ,\r
-CRC_end ,\r
-CRC_out ,\r
-//Ramdon_gen interfac\r
-Random_init ,\r
-RetryCnt ,\r
-Random_time_meet ,\r
-//flow control \r
-pause_apply ,\r
-pause_quanta_sub ,\r
-xoff_gen ,\r
-xoff_gen_complete ,\r
-xon_gen ,\r
-xon_gen_complete ,\r
-//MAC_tx_FF \r
-Fifo_data ,\r
-Fifo_rd ,\r
-Fifo_eop ,\r
-Fifo_da ,\r
-Fifo_rd_finish ,\r
-Fifo_rd_retry ,\r
-Fifo_ra ,\r
-Fifo_data_err_empty ,\r
-Fifo_data_err_full ,\r
-//RMII \r
-TxD ,\r
-TxEn ,\r
-CRS , \r
-//MAC_tx_addr_add \r
-MAC_tx_addr_rd ,\r
-MAC_tx_addr_data ,\r
-MAC_tx_addr_init ,\r
-//RMON \r
-Tx_pkt_type_rmon ,\r
-Tx_pkt_length_rmon ,\r
-Tx_apply_rmon ,\r
-Tx_pkt_err_type_rmon,\r
-//CPU \r
-pause_quanta_set , \r
-MAC_tx_add_en , \r
-FullDuplex ,\r
-MaxRetry ,\r
-IFGset \r
-);\r
-\r
-input Reset ;\r
-input Clk ;\r
- //CRC_gen Interface \r
-output CRC_init ;\r
-output [7:0] Frame_data ;\r
-output Data_en ;\r
-output CRC_rd ;\r
-input CRC_end ;\r
-input [7:0] CRC_out ;\r
- //Ramdon_gen interface\r
-output Random_init ;\r
-output [3:0] RetryCnt ;\r
-input Random_time_meet ;//levle hight indicate random time passed away\r
- //flow control\r
-input pause_apply ;\r
-output pause_quanta_sub ;\r
-input xoff_gen ;\r
-output xoff_gen_complete ;\r
-input xon_gen ;\r
-output xon_gen_complete ; \r
- //MAC_rx_FF\r
-input [7:0] Fifo_data ;\r
-output Fifo_rd ;\r
-input Fifo_eop ;\r
-input Fifo_da ;\r
-output Fifo_rd_finish ;\r
-output Fifo_rd_retry ;\r
-input Fifo_ra ;\r
-input Fifo_data_err_empty ;\r
-input Fifo_data_err_full ;\r
- //RMII\r
-output [7:0] TxD ;\r
-output TxEn ; \r
-input CRS ;\r
- //MAC_tx_addr_add\r
-output MAC_tx_addr_init ;\r
-output MAC_tx_addr_rd ;\r
-input [7:0] MAC_tx_addr_data ;\r
- //RMON\r
-output [2:0] Tx_pkt_type_rmon ;\r
-output [15:0] Tx_pkt_length_rmon ;\r
-output Tx_apply_rmon ;\r
-output [2:0] Tx_pkt_err_type_rmon; \r
- //CPU\r
-input [15:0] pause_quanta_set ;\r
-input MAC_tx_add_en ; \r
-input FullDuplex ;\r
-input [3:0] MaxRetry ;\r
-input [5:0] IFGset ;\r
-//****************************************************************************** \r
-//internal signals \r
-//****************************************************************************** \r
-parameter StateIdle =4'd00;\r
-parameter StatePreamble =4'd01;\r
-parameter StateSFD =4'd02;\r
-parameter StateData =4'd03;\r
-parameter StatePause =4'd04;\r
-parameter StatePAD =4'd05;\r
-parameter StateFCS =4'd06;\r
-parameter StateIFG =4'd07;\r
-parameter StateJam =4'd08;\r
-parameter StateBackOff =4'd09;\r
-parameter StateJamDrop =4'd10;\r
-parameter StateFFEmptyDrop =4'd11;\r
-parameter StateSwitchNext =4'd12;\r
-parameter StateDefer =4'd13;\r
-parameter StateSendPauseFrame =4'd14;\r
-\r
-reg [3:0] Current_state;\r
-reg [3:0] Next_state;\r
-reg [5:0] IFG_counter;\r
-reg [4:0] Preamble_counter;//\r
-reg [7:0] TxD_tmp ; \r
-reg TxEn_tmp ; \r
-reg [15:0] Tx_pkt_length_rmon ;\r
-reg Tx_apply_rmon ;\r
-reg [2:0] Tx_pkt_err_type_rmon; \r
-reg [3:0] RetryCnt ;\r
-reg Random_init ;\r
-reg Fifo_rd_finish ;\r
-reg Fifo_rd_retry ;\r
-reg [7:0] TxD ; \r
-reg TxEn ; \r
-reg CRC_init ;\r
-reg Data_en ;\r
-reg CRC_rd ;\r
-reg Fifo_rd ;\r
-reg MAC_tx_addr_rd ;\r
-reg MAC_header_slot ;\r
-reg MAC_header_slot_tmp ;\r
-reg [2:0] Tx_pkt_type_rmon ;\r
-wire Collision ; \r
-reg MAC_tx_addr_init ;\r
-reg Src_MAC_ptr ;\r
-reg [7:0] IPLengthCounter ;//for pad append\r
-reg [1:0] PADCounter ;\r
-reg [7:0] JamCounter ;\r
-reg PktDrpEvenPtr ;\r
-reg [7:0] pause_counter ;\r
-reg pause_quanta_sub ;\r
-reg [15:0] pause_quanta_set_dl1 ;\r
-reg xoff_gen_complete ;\r
-reg xon_gen_complete ;\r
-//****************************************************************************** \r
-//boundery signal processing \r
-//****************************************************************************** \r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin \r
- pause_quanta_set_dl1 <=0;\r
- end\r
- else\r
- begin \r
- pause_quanta_set_dl1 <=pause_quanta_set ;\r
- end \r
-//****************************************************************************** \r
-//state machine \r
-//****************************************************************************** \r
-assign Collision=TxEn&CRS;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- IPLengthCounter <=0;\r
- else if (Current_state==StateDefer)\r
- IPLengthCounter <=0; \r
- else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD))\r
- IPLengthCounter <=IPLengthCounter+1;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- PADCounter <=0;\r
- else if (Current_state!=StatePAD)\r
- PADCounter <=0;\r
- else\r
- PADCounter <=PADCounter+1;\r
-\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- Current_state <=StateDefer;\r
- else \r
- Current_state <=Next_state; \r
- \r
-always @ (*)\r
- case (Current_state) \r
- StateDefer:\r
- if ((FullDuplex)||(!FullDuplex&&!CRS))\r
- Next_state=StateIFG;\r
- else\r
- Next_state=Current_state; \r
- StateIFG:\r
- if (!FullDuplex&&CRS)\r
- Next_state=StateDefer;\r
- else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time\r
- Next_state=StateIdle;\r
- else\r
- Next_state=Current_state; \r
- StateIdle:\r
- if (!FullDuplex&&CRS)\r
- Next_state=StateDefer;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StatePreamble;\r
- else if (pause_apply)\r
- Next_state=StatePause; \r
- else if ((FullDuplex||~CRS)&&Fifo_ra)\r
- Next_state=StatePreamble;\r
- else\r
- Next_state=Current_state; \r
- StatePause:\r
- if (pause_counter==512/8)\r
- Next_state=StateDefer;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StateIdle;\r
- else\r
- Next_state=Current_state; \r
- StatePreamble:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6))\r
- Next_state=StateSFD;\r
- else\r
- Next_state=Current_state;\r
- StateSFD:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if (xoff_gen||xon_gen)\r
- Next_state=StateSendPauseFrame;\r
- else \r
- Next_state=StateData;\r
- StateSendPauseFrame:\r
- if (IPLengthCounter==17)\r
- Next_state=StatePAD;\r
- else\r
- Next_state=Current_state;\r
- StateData:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam;\r
- else if (Fifo_data_err_empty)\r
- Next_state=StateFFEmptyDrop; \r
- else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0\r
- Next_state=StateFCS;\r
- else if (Fifo_eop)\r
- Next_state=StatePAD;\r
- else \r
- Next_state=StateData; \r
- StatePAD:\r
- if (!FullDuplex&&Collision)\r
- Next_state=StateJam; \r
- else if (IPLengthCounter>=59)\r
- Next_state=StateFCS; \r
- else \r
- Next_state=Current_state;\r
- StateJam:\r
- if (RetryCnt<=MaxRetry&&JamCounter==16) \r
- Next_state=StateBackOff;\r
- else if (RetryCnt>MaxRetry)\r
- Next_state=StateJamDrop;\r
- else\r
- Next_state=Current_state;\r
- StateBackOff:\r
- if (Random_time_meet)\r
- Next_state =StateDefer;\r
- else \r
- Next_state =Current_state;\r
- StateFCS:\r
- if (!FullDuplex&&Collision)\r
- Next_state =StateJam;\r
- else if (CRC_end)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state;\r
- StateFFEmptyDrop:\r
- if (Fifo_eop)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state; \r
- StateJamDrop:\r
- if (Fifo_eop)\r
- Next_state =StateSwitchNext;\r
- else\r
- Next_state =Current_state;\r
- StateSwitchNext:\r
- Next_state =StateDefer; \r
- default:\r
- Next_state =StateDefer;\r
- endcase\r
-\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- JamCounter <=0;\r
- else if (Current_state!=StateJam)\r
- JamCounter <=0;\r
- else if (Current_state==StateJam)\r
- JamCounter <=JamCounter+1;\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- RetryCnt <=0;\r
- else if (Current_state==StateSwitchNext)\r
- RetryCnt <=0;\r
- else if (Current_state==StateJam&&Next_state==StateBackOff)\r
- RetryCnt <=RetryCnt + 1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- IFG_counter <=0;\r
- else if (Current_state!=StateIFG)\r
- IFG_counter <=0;\r
- else \r
- IFG_counter <=IFG_counter + 1;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Preamble_counter <=0;\r
- else if (Current_state!=StatePreamble)\r
- Preamble_counter <=0;\r
- else\r
- Preamble_counter <=Preamble_counter+ 1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- PktDrpEvenPtr <=0;\r
- else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)\r
- PktDrpEvenPtr <=~PktDrpEvenPtr;\r
-//****************************************************************************** \r
-//generate output signals \r
-//****************************************************************************** \r
-//CRC related\r
-always @(Current_state)\r
- if (Current_state==StateSFD)\r
- CRC_init =1;\r
- else\r
- CRC_init =0;\r
- \r
-assign Frame_data=TxD_tmp;\r
-\r
-always @(Current_state)\r
- if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)\r
- Data_en =1;\r
- else\r
- Data_en =0;\r
- \r
-always @(Current_state)\r
- if (Current_state==StateFCS)\r
- CRC_rd =1;\r
- else\r
- CRC_rd =0; \r
- \r
-//Ramdon_gen interface\r
-always @(Current_state or Next_state)\r
- if (Current_state==StateJam&&Next_state==StateBackOff)\r
- Random_init =1;\r
- else\r
- Random_init =0; \r
-\r
-//MAC_rx_FF\r
-//data have one cycle delay after fifo read signals \r
-always @ (*)\r
- if (Current_state==StateData ||\r
- Current_state==StateSFD&&!(xoff_gen||xon_gen) ||\r
- Current_state==StateJamDrop&&PktDrpEvenPtr||\r
- Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )\r
- Fifo_rd =1;\r
- else\r
- Fifo_rd =0; \r
- \r
-always @ (Current_state)\r
- if (Current_state==StateSwitchNext) \r
- Fifo_rd_finish =1;\r
- else\r
- Fifo_rd_finish =0;\r
- \r
-always @ (Current_state)\r
- if (Current_state==StateJam) \r
- Fifo_rd_retry =1;\r
- else\r
- Fifo_rd_retry =0; \r
-//RMII\r
-always @(Current_state)\r
- if (Current_state==StatePreamble||Current_state==StateSFD||\r
- Current_state==StateData||Current_state==StateSendPauseFrame||\r
- Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)\r
- TxEn_tmp =1;\r
- else\r
- TxEn_tmp =0;\r
-\r
-//gen txd data \r
-always @(*)\r
- case (Current_state)\r
- StatePreamble:\r
- TxD_tmp =8'h55;\r
- StateSFD:\r
- TxD_tmp =8'hd5;\r
- StateData:\r
- if (Src_MAC_ptr&&MAC_tx_add_en) \r
- TxD_tmp =MAC_tx_addr_data;\r
- else\r
- TxD_tmp =Fifo_data;\r
- StateSendPauseFrame:\r
- if (Src_MAC_ptr&&MAC_tx_add_en) \r
- TxD_tmp =MAC_tx_addr_data;\r
- else \r
- case (IPLengthCounter)\r
- 8'd0: TxD_tmp =8'h01;\r
- 8'd1: TxD_tmp =8'h80;\r
- 8'd2: TxD_tmp =8'hc2;\r
- 8'd3: TxD_tmp =8'h00;\r
- 8'd4: TxD_tmp =8'h00;\r
- 8'd5: TxD_tmp =8'h01;\r
- 8'd12: TxD_tmp =8'h88;//type\r
- 8'd13: TxD_tmp =8'h08;//\r
- 8'd14: TxD_tmp =8'h00;//opcode\r
- 8'd15: TxD_tmp =8'h01;\r
- 8'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];\r
- 8'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];\r
-// 8'd60: TxD_tmp =8'h26;\r
-// 8'd61: TxD_tmp =8'h6b;\r
-// 8'd62: TxD_tmp =8'hae;\r
-// 8'd63: TxD_tmp =8'h0a;\r
- default:TxD_tmp =0;\r
- endcase\r
- \r
- StatePAD:\r
- TxD_tmp =8'h00; \r
- StateJam:\r
- TxD_tmp =8'h01; //jam sequence\r
- StateFCS:\r
- TxD_tmp =CRC_out;\r
- default:\r
- TxD_tmp =2'b0;\r
- endcase\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- begin\r
- TxD <=0;\r
- TxEn <=0;\r
- end\r
- else\r
- begin\r
- TxD <=TxD_tmp;\r
- TxEn <=TxEn_tmp;\r
- end \r
-//RMON\r
-\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_length_rmon <=0;\r
- else if (Current_state==StateSFD)\r
- Tx_pkt_length_rmon <=0;\r
- else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)\r
- Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;\r
- \r
-\r
-reg [2:0] Tx_apply_rmon_reg;\r
-\r
-always @( posedge Clk or posedge Reset )\r
- if ( Reset )\r
- begin\r
- Tx_apply_rmon <= 0;\r
- Tx_apply_rmon_reg <= 'b0;\r
- end\r
- else\r
- begin\r
- if ( (Fifo_eop&&Current_state==StateJamDrop) ||\r
- (Fifo_eop&&Current_state==StateFFEmptyDrop) ||\r
- CRC_end )\r
- Tx_apply_rmon <= 1;\r
- else\r
- if ( Tx_apply_rmon_reg[2] )\r
- Tx_apply_rmon <= 0;\r
-\r
- Tx_apply_rmon_reg <= { Tx_apply_rmon_reg[1:0], Tx_apply_rmon };\r
- end\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_err_type_rmon <=0; \r
- else if(Fifo_eop&&Current_state==StateJamDrop)\r
- Tx_pkt_err_type_rmon <=3'b001;//\r
- else if(Fifo_eop&&Current_state==StateFFEmptyDrop)\r
- Tx_pkt_err_type_rmon <=3'b010;//underflow\r
- else if(Fifo_eop&&Fifo_data_err_full)\r
- Tx_pkt_err_type_rmon <=3'b011;//overflow\r
- else if(CRC_end)\r
- Tx_pkt_err_type_rmon <=3'b100;//normal\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_header_slot_tmp <=0;\r
- else if(Current_state==StateSFD&&Next_state==StateData)\r
- MAC_header_slot_tmp <=1; \r
- else\r
- MAC_header_slot_tmp <=0;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_header_slot <=0;\r
- else \r
- MAC_header_slot <=MAC_header_slot_tmp;\r
-\r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- Tx_pkt_type_rmon <=0;\r
- else if (Current_state==StateSendPauseFrame)\r
- Tx_pkt_type_rmon <=3'b100;\r
- else if(MAC_header_slot)\r
- Tx_pkt_type_rmon <={1'b0,TxD[7:6]};\r
-\r
- \r
-always @(Tx_pkt_length_rmon)\r
- if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)\r
- Src_MAC_ptr =1;\r
- else\r
- Src_MAC_ptr =0; \r
-\r
-//MAC_tx_addr_add \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- MAC_tx_addr_rd <=0;\r
- else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))\r
- MAC_tx_addr_rd <=1;\r
- else\r
- MAC_tx_addr_rd <=0;\r
-\r
- always @*\r
- //if ((Tx_pkt_length_rmon==3)&&Fifo_rd)\r
- if (Current_state==StatePreamble)\r
- MAC_tx_addr_init=1;\r
- else\r
- MAC_tx_addr_init=0;\r
-\r
-//**************************************************************************************************************\r
-// CFH: this implementation delays the time it sends an entire Ethernet frame with 512 bits for every pause\r
-// request of 512 bits. Actually, it should only delay the time it takes to transmit 512 bits, not counting\r
-// Ethernet header, CRC, Interframe Gap etc.\r
-// Hence the current implementation waits longer than the pause frame actually requests (~20% more)\r
-//**************************************************************************************************************\r
-\r
-//flow control\r
-always @(posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_counter <=0;\r
- else if (Current_state!=StatePause)\r
- pause_counter <=0;\r
- else \r
- pause_counter <=pause_counter+1;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset)\r
- pause_quanta_sub <=0;\r
- else if(pause_counter==512/8)\r
- pause_quanta_sub <=1;\r
- else\r
- pause_quanta_sub <=0;\r
-\r
-// FIXME The below probably won't work if the pause request comes when we are in the wrong state\r
- reg clear_xonxoff;\r
- always @(posedge Clk or posedge Reset)\r
- if(Reset)\r
- clear_xonxoff <= 0;\r
- else if((Current_state==StateSendPauseFrame) & (IPLengthCounter==17))\r
- clear_xonxoff <= 1;\r
- else if(~xon_gen & ~xoff_gen)\r
- clear_xonxoff <= 0;\r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- xoff_gen_complete <=0;\r
- else if(clear_xonxoff & xoff_gen)\r
- xoff_gen_complete <=1;\r
- else\r
- xoff_gen_complete <=0;\r
- \r
- \r
-always @ (posedge Clk or posedge Reset)\r
- if (Reset) \r
- xon_gen_complete <=0;\r
- else if(clear_xonxoff & xon_gen)\r
- xon_gen_complete <=1;\r
- else\r
- xon_gen_complete <=0;\r
-\r
-endmodule\r
projects / debian / gnuradio / blobdiff