+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// MAC_rx.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: MAC_rx.v,v $\r
-// Revision 1.4 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.3 2006/01/19 14:07:52 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:13 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module MAC_rx \r
- #(parameter RX_FF_DEPTH = 9)\r
- (\r
-input Reset ,\r
-input Clk_user,\r
-input Clk ,\r
- //RMII interface\r
-input MCrs_dv , \r
-input [7:0] MRxD , \r
-input MRxErr , \r
- //flow_control signals \r
-output [15:0] pause_quanta, \r
-output pause_quanta_val, \r
-output [15:0] rx_fifo_space,\r
- //user interface \r
-output Rx_mac_empty,\r
-input Rx_mac_rd ,\r
-output [31:0] Rx_mac_data ,\r
-output [1:0] Rx_mac_BE ,\r
-output Rx_mac_sop ,\r
-output Rx_mac_eop ,\r
-output Rx_mac_err ,\r
- //CPU\r
-input MAC_rx_add_chk_en , \r
-input [7:0] MAC_add_prom_data , \r
-input [2:0] MAC_add_prom_add , \r
-input MAC_add_prom_wr , \r
-input broadcast_filter_en ,\r
-input [15:0] broadcast_bucket_depth , \r
-input [15:0] broadcast_bucket_interval ,\r
-input RX_APPEND_CRC,\r
-input [4:0] Rx_Hwmark ,\r
-input [4:0] Rx_Lwmark ,\r
-input CRC_chk_en , \r
-input [5:0] RX_IFG_SET ,\r
-input [15:0] RX_MAX_LENGTH ,// 1518\r
-input [6:0] RX_MIN_LENGTH ,// 64\r
- //RMON interface\r
-output [15:0] Rx_pkt_length_rmon ,\r
-output Rx_apply_rmon ,\r
-output [2:0] Rx_pkt_err_type_rmon ,\r
-output [2:0] Rx_pkt_type_rmon ,\r
-\r
- output [15:0] rx_fifo_occupied,\r
- output rx_fifo_full,\r
- output rx_fifo_empty,\r
- output [31:0] debug\r
-);\r
-//******************************************************************************\r
-//internal signals \r
-//******************************************************************************\r
- //CRC_chk interface\r
-wire CRC_en ; \r
-wire [7:0] CRC_data;\r
-wire CRC_init; \r
-wire CRC_err ;\r
- //MAC_rx_add_chk interface\r
-wire MAC_add_en ;\r
-wire [7:0] MAC_add_data;\r
-wire MAC_rx_add_chk_err ;\r
- //broadcast_filter\r
-wire broadcast_ptr ;\r
-wire broadcast_drop ;\r
- //MAC_rx_ctrl interface \r
-wire [7:0] Fifo_data ;\r
-wire Fifo_data_en ;\r
-wire Fifo_full ;\r
-wire Fifo_data_err ;\r
-wire Fifo_data_drop ;\r
-wire Fifo_data_end ;\r
-\r
-\r
-//******************************************************************************\r
-//instantiation \r
-//******************************************************************************\r
-\r
-\r
-MAC_rx_ctrl U_MAC_rx_ctrl(\r
-.Reset (Reset ), \r
-.Clk (Clk ), \r
- //RMII interface ( //RMII interface ), \r
-.MCrs_dv (MCrs_dv ), \r
-.MRxD (MRxD ), \r
-.MRxErr (MRxErr ), \r
- //CRC_chk interface (//CRC_chk interface ), \r
-.CRC_en (CRC_en ), \r
-.CRC_data (CRC_data ), \r
-.CRC_init (CRC_init ), \r
-.CRC_err (CRC_err ), \r
- //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), \r
-.MAC_add_en (MAC_add_en ), \r
-.MAC_add_data (MAC_add_data ),\r
-.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), \r
- //broadcast_filter (//broadcast_filter ), \r
-.broadcast_ptr (broadcast_ptr ), \r
-.broadcast_drop (broadcast_drop ), \r
- //flow_control signals (//flow_control signals ), \r
-.pause_quanta (pause_quanta ), \r
-.pause_quanta_val (pause_quanta_val ), \r
- //MAC_rx_FF interface (//MAC_rx_FF interface ), \r
-.Fifo_data (Fifo_data ), \r
-.Fifo_data_en (Fifo_data_en ), \r
-.Fifo_data_err (Fifo_data_err ), \r
-.Fifo_data_drop (Fifo_data_drop ), \r
-.Fifo_data_end (Fifo_data_end ), \r
-.Fifo_full (Fifo_full ), \r
- //RMON interface (//RMON interface ), \r
-.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), \r
-.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), \r
-.Rx_apply_rmon (Rx_apply_rmon ), \r
-.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), \r
- //CPU (//CPU ), \r
-.RX_IFG_SET (RX_IFG_SET ), \r
-.RX_MAX_LENGTH (RX_MAX_LENGTH ), \r
-.RX_MIN_LENGTH (RX_MIN_LENGTH ) \r
-);\r
-\r
- assign debug = {28'd0, Fifo_data_en, Fifo_data_err, Fifo_data_end,Fifo_full};\r
- \r
-MAC_rx_FF #(.RX_FF_DEPTH(RX_FF_DEPTH)) U_MAC_rx_FF (\r
-.Reset (Reset ),\r
-.Clk_MAC (Clk ), \r
-.Clk_SYS (Clk_user ), \r
- //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),\r
-.Fifo_data (Fifo_data ),\r
-.Fifo_data_en (Fifo_data_en ),\r
-.Fifo_full (Fifo_full ),\r
-.Fifo_data_err (Fifo_data_err ),\r
-//.Fifo_data_drop (Fifo_data_drop ),\r
-.Fifo_data_end (Fifo_data_end ),\r
-.Fifo_space (rx_fifo_space ), \r
- //CPU (//CPU ),\r
-.Rx_Hwmark (Rx_Hwmark ),\r
-.Rx_Lwmark (Rx_Lwmark ),\r
-.RX_APPEND_CRC (RX_APPEND_CRC ),\r
- //user interface (//user interface ),\r
-.Rx_mac_empty (Rx_mac_empty ),\r
-.Rx_mac_rd (Rx_mac_rd ),\r
-.Rx_mac_data (Rx_mac_data ), \r
-.Rx_mac_BE (Rx_mac_BE ),\r
-.Rx_mac_sop (Rx_mac_sop ), \r
-.Rx_mac_eop (Rx_mac_eop ),\r
-.Rx_mac_err (Rx_mac_err ),\r
-\r
-.fifo_occupied(rx_fifo_occupied),\r
-.fifo_full_dbg(rx_fifo_full),\r
-.fifo_empty(rx_fifo_empty)\r
-); \r
-\r
- Broadcast_filter U_Broadcast_filter\r
- (.Reset (Reset ),\r
- .Clk (Clk ),\r
- //MAC_rx_ctrl (//MAC_rx_ctrl ),\r
- .broadcast_ptr (broadcast_ptr ),\r
- .broadcast_drop (broadcast_drop ),\r
- //FromCPU (//FromCPU ),\r
- .broadcast_filter_en (broadcast_filter_en ),\r
- .broadcast_bucket_depth (broadcast_bucket_depth ), \r
- .broadcast_bucket_interval (broadcast_bucket_interval )\r
- ); \r
- \r
-CRC_chk U_CRC_chk(\r
-.Reset (Reset ),\r
-.Clk (Clk ),\r
-.CRC_data (CRC_data ),\r
-.CRC_init (CRC_init ),\r
-.CRC_en (CRC_en ),\r
- //From CPU (//From CPU ),\r
-.CRC_chk_en (CRC_chk_en ),\r
-.CRC_err (CRC_err )\r
-); \r
- \r
- MAC_rx_add_chk U_MAC_rx_add_chk\r
- (.Reset (Reset ),\r
- .Clk (Clk ),\r
- .Init (CRC_init ),\r
- .data (MAC_add_data ),\r
- .MAC_add_en (MAC_add_en ),\r
- .MAC_rx_add_chk_err (MAC_rx_add_chk_err ),\r
- //From CPU (//From CPU ),\r
- .MAC_rx_add_chk_en (MAC_rx_add_chk_en ),\r
- .MAC_add_prom_data (MAC_add_prom_data ),\r
- .MAC_add_prom_add (MAC_add_prom_add ),\r
- .MAC_add_prom_wr (MAC_add_prom_wr )\r
- );\r
- \r
-endmodule // MAC_rx\r
projects / debian / gnuradio / blobdiff