+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Clk_ctrl.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: Clk_ctrl.v,v $\r
-// Revision 1.3 2006/01/19 14:07:52 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/16 06:44:13 Administrator\r
-// replaced tab with space.\r
-// passed 9.6k length frame test.\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-\r
-module Clk_ctrl( \r
-Reset ,\r
-Clk_125M ,\r
-//host interface,\r
-Speed ,\r
-//Phy interface ,\r
-Gtx_clk ,\r
-Rx_clk ,\r
-Tx_clk ,\r
-//interface clk ,\r
-MAC_tx_clk ,\r
-MAC_rx_clk ,\r
-MAC_tx_clk_div ,\r
-MAC_rx_clk_div \r
-);\r
-input Reset ;\r
-input Clk_125M ;\r
- //host interface\r
-input [2:0] Speed ; \r
- //Phy interface \r
-output Gtx_clk ;//used only in GMII mode\r
-input Rx_clk ;\r
-input Tx_clk ;//used only in MII mode\r
- //interface clk signals\r
-output MAC_tx_clk ;\r
-output MAC_rx_clk ;\r
-output MAC_tx_clk_div ;\r
-output MAC_rx_clk_div ;\r
-\r
-\r
-// ******************************************************************************\r
-// internal signals \r
-// ******************************************************************************\r
-wire Rx_clk_div2 ;\r
-wire Tx_clk_div2 ;\r
-// ******************************************************************************\r
-// \r
-// ******************************************************************************\r
- assign Gtx_clk = Clk_125M ;\r
- assign MAC_rx_clk = Rx_clk ;\r
- assign MAC_rx_clk_div = Rx_clk ;\r
- assign MAC_tx_clk = Clk_125M;\r
- assign MAC_tx_clk_div = Clk_125M;\r
- \r
-\r
- /* \r
-eth_clk_div2 U_0_CLK_DIV2(\r
-.Reset (Reset ),\r
-.IN (Rx_clk ),\r
-.OUT (Rx_clk_div2 )\r
-);\r
-\r
-eth_clk_div2 U_1_CLK_DIV2(\r
-.Reset (Reset ),\r
-.IN (Tx_clk ),\r
-.OUT (Tx_clk_div2 )\r
-);\r
-\r
-eth_clk_switch U_0_CLK_SWITCH(\r
-.IN_0 (Rx_clk_div2 ),\r
-.IN_1 (Rx_clk ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_rx_clk_div )\r
-);\r
-\r
-eth_clk_switch U_1_CLK_SWITCH(\r
-.IN_0 (Tx_clk ),\r
-.IN_1 (Clk_125M ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_tx_clk )\r
-);\r
-\r
-eth_clk_switch U_2_CLK_SWITCH(\r
-.IN_0 (Tx_clk_div2 ),\r
-.IN_1 (Clk_125M ),\r
-.SW (Speed[2] ),\r
-.OUT (MAC_tx_clk_div )\r
-);\r
-\r
- */\r
-endmodule\r
projects / debian / gnuradio / blobdiff