+++ /dev/null
-module demo(\r
- Reset_n,\r
- Clk_100M,\r
- Clk_125M, // GMII only\r
-\r
- RS232_TXD,\r
- RS232_RXD,\r
-\r
- USB_TXD,\r
- USB_RXD,\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- PHY_RESET_n,\r
-\r
- PHY_RXC,\r
- PHY_RXD,\r
- PHY_RXDV,\r
- PHY_RXER,\r
-\r
- PHY_GTX_CLK, // GMII only\r
- PHY_TXC,\r
- PHY_TXD,\r
- PHY_TXEN,\r
- PHY_TXER,\r
-\r
- PHY_COL,\r
- PHY_CRS,\r
-\r
- PHY_MDC,\r
- PHY_MDIO,\r
-\r
- // Misc. I/Os\r
- LED,\r
- Button\r
-);\r
-\r
- input Reset_n;\r
- input Clk_100M;\r
- input Clk_125M; // GMII\r
-\r
- output RS232_TXD;\r
- input RS232_RXD;\r
-\r
- output USB_TXD;\r
- input USB_RXD;\r
-\r
- //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII)\r
- output PHY_RESET_n;\r
-\r
- input PHY_RXC;\r
- input [7:0] PHY_RXD;\r
- input PHY_RXDV;\r
- input PHY_RXER;\r
-\r
- output PHY_GTX_CLK; // GMII only\r
- input PHY_TXC;\r
- output [7:0] PHY_TXD;\r
- output PHY_TXEN;\r
- output PHY_TXER;\r
-\r
- input PHY_COL;\r
- input PHY_CRS;\r
-\r
- output PHY_MDC;\r
- inout PHY_MDIO;\r
-\r
- // Misc. I/Os\r
- output [1:4] LED;\r
-\r
- input [1:4] Button;\r
-\r
- //-------------------------------------------------------------------------\r
- // Local declarations\r
- //-------------------------------------------------------------------------\r
-\r
- // Rename to "standard" core clock name\r
- wire Clk = Clk_100M;\r
-\r
- reg [27:0] Counter;\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- Counter <= 0;\r
- else\r
- Counter <= Counter + 1;\r
-\r
- assign LED[1:4] = Counter[27:24];\r
-\r
- //-------------------------------------------------------------------------\r
- // Instantiation of sub-modules\r
- //-------------------------------------------------------------------------\r
-\r
- //--- UART ----------------------------------------------------------------\r
-\r
- wire UART_RXD;\r
- wire UART_TXD;\r
- wire UART_RxValid;\r
- wire [7:0] UART_RxData;\r
- wire UART_TxReady;\r
- wire UART_TxValid;\r
- wire [7:0] UART_TxData;\r
-\r
- demo_uart demo_uart(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- // Interface to UART PHY\r
- .RXD_i( UART_RXD ),\r
- .TXD_o( UART_TXD ),\r
-\r
- // Clk is divided by (Prescaler+1) to generate 16x the bitrate\r
-`ifdef EHDL_SIMULATION\r
- .Prescaler_i( 16'd3 ), // Corresponds to VERY FAST - for simulation only!\r
-`else \r
- .Prescaler_i( 16'd650 ), // Corresponds to 9600 baud (assuming 100 MHz clock)\r
-`endif\r
- \r
- // Pulsed when RxData is valid\r
- .RxValid_o( UART_RxValid ),\r
- .RxData_o ( UART_RxData ),\r
-\r
- // Asserted when ready for a new Tx byte\r
- .TxReady_o( UART_TxReady ),\r
-\r
- // Pulsed when TxData is valid\r
- .TxValid_i( UART_TxValid ),\r
- .TxData_i ( UART_TxData )\r
- );\r
-\r
- // Transmit & receive in parallel on either RS232 or USB/RS232 interface\r
-// assign UART_RXD = RS232_RXD & USB_RXD; // RS232 signals are high when inactive\r
- assign UART_RXD = RS232_RXD;\r
-\r
- assign RS232_TXD = UART_TXD;\r
- assign USB_TXD = UART_TXD;\r
-\r
- //--- UART-to-Wishbone Master ---------------------------------------------\r
-\r
- wire WB_STB_ETH;\r
- wire WB_STB_PDM;\r
- wire WB_STB_PG;\r
- wire WB_CYC;\r
- wire [14:0] WB_ADR;\r
- wire WB_WE;\r
- wire [15:0] WB_DAT_Wr;\r
- wire [15:0] WB_DAT_Rd;\r
- wire WB_ACK;\r
-\r
- demo_wishbone_master demo_wishbone_master(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- UART interface\r
-\r
- // Pulsed when RxData_i is valid\r
- .RxValid_i( UART_RxValid ),\r
- .RxData_i ( UART_RxData ),\r
-\r
- // Asserted when ready for a new Tx byte\r
- .TxReady_i( UART_TxReady ),\r
-\r
- // Pulsed when TxData_o is valid\r
- .TxValid_o( UART_TxValid ),\r
- .TxData_o ( UART_TxData ),\r
-\r
- //--- Wishbone interface\r
- .STB_ETH_O( WB_STB_ETH ),\r
- .STB_PDM_O( WB_STB_PDM ),\r
- .STB_PG_O ( WB_STB_PG ),\r
- .CYC_O ( WB_CYC ),\r
- .ADR_O ( WB_ADR ),\r
- .WE_O ( WB_WE ), \r
- .DAT_O ( WB_DAT_Wr ),\r
- .DAT_I ( WB_DAT_Rd ),\r
- .ACK_I ( WB_ACK )\r
- );\r
-\r
- //--- Wishbone clients ----------------------------------------------------\r
-\r
- //--- Packet Descriptor Memory --------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_PDM;\r
- wire WB_ACK_PDM;\r
-\r
- wire PDM_Rd;\r
- wire [13:0] PDM_Addr;\r
- wire [31:0] PDM_RdData;\r
-\r
- demo_packet_descriptor_memory demo_packet_descriptor_memory(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- Wishbone interface\r
- .STB_I( WB_STB_PDM ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR ),\r
- .WE_I ( WB_WE ), \r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_PDM ),\r
- .ACK_O( WB_ACK_PDM ),\r
-\r
- //--- Packet Generator interface\r
- // RdData_o is always valid exactly one clock after Addr_i changes\r
- // and Rd_i is asserted\r
- .Rd_i ( PDM_Rd ),\r
- .Addr_i ( PDM_Addr ),\r
- .RdData_o( PDM_RdData )\r
- );\r
-\r
- //--- Packet Generator ----------------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_PG;\r
- wire WB_ACK_PG;\r
-\r
- wire Rx_mac_ra;\r
- wire Rx_mac_rd;\r
- wire [31:0] Rx_mac_data;\r
- wire [1:0] Rx_mac_BE;\r
- wire Rx_mac_pa;\r
- wire Rx_mac_sop;\r
- wire Rx_mac_err;\r
- wire Rx_mac_eop;\r
-\r
- wire Tx_mac_wa;\r
- wire Tx_mac_wr;\r
- wire [31:0] Tx_mac_data;\r
- wire [1:0] Tx_mac_BE;\r
- wire Tx_mac_sop;\r
- wire Tx_mac_eop;\r
-\r
- demo_packet_generator demo_packet_generator(\r
- .Reset_n( Reset_n ),\r
- .Clk ( Clk ),\r
-\r
- //--- Wishbone interface\r
- .STB_I( WB_STB_PG ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR[1:0] ),\r
- .WE_I ( WB_WE ),\r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_PG ),\r
- .ACK_O( WB_ACK_PG ),\r
-\r
- //--- Packet Descriptor Memory interface\r
- // RdData_i is always valid exactly one clock after Addr_o changes\r
- // and Rd_o is asserted\r
- .Rd_o ( PDM_Rd ),\r
- .Addr_o ( PDM_Addr ),\r
- .RdData_i( PDM_RdData ),\r
-\r
- //--- User (packet) interface\r
- .Rx_mac_ra ( Rx_mac_ra ),\r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_pa ( Rx_mac_pa ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
-\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop )\r
- );\r
-\r
- //--- Simple Wishbone client ----------------------------------------------\r
-\r
- reg [15:0] Reg1;\r
- reg [15:0] Reg2;\r
-\r
- reg WB_ACK_Reg;\r
- reg [15:0] WB_DAT_Reg;\r
-\r
- always @( negedge Reset_n or posedge Clk )\r
- if ( ~Reset_n )\r
- begin\r
- WB_ACK_Reg <= 0;\r
- WB_DAT_Reg <= 'b0;\r
-\r
- Reg1 <= 16'h1234;\r
- Reg2 <= 16'hABCD;\r
- end\r
- else\r
- begin\r
- WB_ACK_Reg <= 0;\r
- if ( WB_CYC & ~( WB_STB_ETH | WB_STB_PG | WB_STB_PDM ) )\r
- begin\r
- WB_ACK_Reg <= 1;\r
- if ( WB_WE )\r
- begin\r
- if ( WB_ADR[0] )\r
- Reg2 <= WB_DAT_Wr;\r
- else\r
- Reg1 <= WB_DAT_Wr;\r
- end\r
- else\r
- begin\r
- if ( WB_ADR[0] )\r
- WB_DAT_Reg <= Reg2;\r
- else\r
- WB_DAT_Reg <= Reg1;\r
- end\r
- end\r
- end\r
-\r
- //--- DUT - Ethernet Core -------------------------------------------------\r
-\r
- wire [15:0] WB_DAT_Rd_ETH;\r
- wire WB_ACK_ETH;\r
-\r
- wire [2:0] Speed;\r
-\r
- MAC_top dut(\r
- // System signals\r
- .Clk_125M( Clk_125M ),\r
- .Clk_user( Clk ),\r
- .Speed ( Speed ),\r
-\r
- // Wishbone compliant core host interface\r
- .RST_I( ~Reset_n ),\r
- .CLK_I( Clk ),\r
- .STB_I( WB_STB_ETH ),\r
- .CYC_I( WB_CYC ),\r
- .ADR_I( WB_ADR[6:0] ),\r
- .WE_I ( WB_WE ),\r
- .DAT_I( WB_DAT_Wr ),\r
- .DAT_O( WB_DAT_Rd_ETH ),\r
- .ACK_O( WB_ACK_ETH ),\r
-\r
- // User (packet) interface\r
- .Rx_mac_ra ( Rx_mac_ra ),\r
- .Rx_mac_rd ( Rx_mac_rd ),\r
- .Rx_mac_data( Rx_mac_data ),\r
- .Rx_mac_BE ( Rx_mac_BE ),\r
- .Rx_mac_pa ( Rx_mac_pa ),\r
- .Rx_mac_sop ( Rx_mac_sop ),\r
- .Rx_mac_err ( Rx_mac_err ),\r
- .Rx_mac_eop ( Rx_mac_eop ),\r
-\r
- .Tx_mac_wa ( Tx_mac_wa ),\r
- .Tx_mac_wr ( Tx_mac_wr ),\r
- .Tx_mac_data( Tx_mac_data ),\r
- .Tx_mac_BE ( Tx_mac_BE ),\r
- .Tx_mac_sop ( Tx_mac_sop ),\r
- .Tx_mac_eop ( Tx_mac_eop ),\r
-\r
- // PHY interface (GMII/MII)\r
- .Gtx_clk( PHY_GTX_CLK ), // Used only in GMII mode\r
- .Rx_clk ( PHY_RXC ),\r
- .Tx_clk ( PHY_TXC ), // Used only in MII mode\r
- .Tx_er ( PHY_TXER ),\r
- .Tx_en ( PHY_TXEN ),\r
- .Txd ( PHY_TXD ),\r
- .Rx_er ( PHY_RXER ),\r
- .Rx_dv ( PHY_RXDV ),\r
- .Rxd ( PHY_RXD ),\r
- .Crs ( PHY_CRS ),\r
- .Col ( PHY_COL ),\r
-\r
- // MDIO interface (to PHY)\r
- .Mdio( PHY_MDIO ),\r
- .Mdc ( PHY_MDC )\r
- );\r
-\r
- //--- Combination of Wishbone read data and acknowledge -------------------\r
-\r
- assign WB_DAT_Rd = ({16{WB_ACK_Reg}} & WB_DAT_Reg ) |\r
- ({16{WB_ACK_PDM}} & WB_DAT_Rd_PDM) |\r
- ({16{WB_ACK_PG }} & WB_DAT_Rd_PG ) |\r
- ({16{WB_ACK_ETH}} & WB_DAT_Rd_ETH);\r
-\r
- assign WB_ACK = WB_ACK_Reg | WB_ACK_PDM | WB_ACK_PG | WB_ACK_ETH;\r
-\r
- assign PHY_RESET_n = Reset_n; \r
-\r
-endmodule\r
projects / debian / gnuradio / blobdiff