Merge branch 'new_eth' of http://gnuradio.org/git/matt into master

[debian/gnuradio] / usrp2 / fpga / eth / bench / verilog / txmac.scr

diff --git a/usrp2/fpga/eth/bench/verilog/txmac.scr b/usrp2/fpga/eth/bench/verilog/txmac.scr
deleted file mode 100644 (file)
index caa7db5..0000000
--- a/usrp2/fpga/eth/bench/verilog/txmac.scr
+++ /dev/null
@@ -1,93 +0,0 @@
-// Read from register 24 to confirm that Rx CRC check is enabled\r
-03 00 18 00 01 ff ff\r
-\r
-// Set speed to 1000 Mbps\r
-01 00 22 00 04\r
-\r
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer\r
-01 00 10 00 00\r
-01 00 0f 00 12\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 01\r
-01 00 0f 00 34\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 02\r
-01 00 0f 00 56\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 03\r
-01 00 0f 00 78\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 04\r
-01 00 0f 00 9A\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-01 00 10 00 05\r
-01 00 0f 00 BC\r
-01 00 11 00 01\r
-01 00 11 00 00\r
-\r
-// Write 1 to register 14, MAC_rx_add_chk_en\r
-// This turns on the Rx Destination MAC address filter\r
-01 00 0e 00 01\r
-\r
-// Setup Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800\r
-// (i.e. Destination MAC address is 123456789ABC matching the above)\r
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00\r
-\r
-// Setup Alternate Tx and Rx MAC addresses and type field to "IP"\r
-// Set Tx Data at offset 0, length 14 to 123456789ABC 112233445566 0800\r
-// (i.e. Destination MAC address is 123456789ABC matching the above)\r
-11 00 00 00 0E 12 34 56 78 9A BC 11 22 33 44 55 66 08 00\r
-\r
-// Transmit a 60-byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Write MAC address 11 22 33 44 55 66 to Tx MAC Source Address buffer\r
-01 00 09 00 00\r
-01 00 08 00 11\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 01\r
-01 00 08 00 22\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 02\r
-01 00 08 00 33\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 03\r
-01 00 08 00 44\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 04\r
-01 00 08 00 55\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-01 00 09 00 05\r
-01 00 08 00 66\r
-01 00 0a 00 01\r
-01 00 0a 00 00\r
-\r
-// Transmit a 60 byte frame 3 times - and expect them to be received again!\r
-20 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r
-\r
-// Write 1 to register 7, MAC_tx_add_en\r
-// This turns on the Tx Source MAC address replacement mechanism\r
-01 00 07 00 01\r
-\r
-// Transmit a 60 byte frame 3 times - and expect them to be received again with Alternate header!\r
-26 00 3C 00 03\r
-\r
-// Wait (indefinitely) for missing Rx packets\r
-22 00 00 \r