+++ /dev/null
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// User_input_sim.v ////\r
-//// ////\r
-//// This file is part of the Ethernet IP core project ////\r
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////\r
-//// ////\r
-//// Author(s): ////\r
-//// - Jon Gao (gaojon@yahoo.com) ////\r
-//// ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-//// ////\r
-//// Copyright (C) 2001 Authors ////\r
-//// ////\r
-//// This source file may be used and distributed without ////\r
-//// restriction provided that this copyright statement is not ////\r
-//// removed from the file and that any derivative work contains ////\r
-//// the original copyright notice and the associated disclaimer. ////\r
-//// ////\r
-//// This source file is free software; you can redistribute it ////\r
-//// and/or modify it under the terms of the GNU Lesser General ////\r
-//// Public License as published by the Free Software Foundation; ////\r
-//// either version 2.1 of the License, or (at your option) any ////\r
-//// later version. ////\r
-//// ////\r
-//// This source is distributed in the hope that it will be ////\r
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\r
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\r
-//// PURPOSE. See the GNU Lesser General Public License for more ////\r
-//// details. ////\r
-//// ////\r
-//// You should have received a copy of the GNU Lesser General ////\r
-//// Public License along with this source; if not, download it ////\r
-//// from http://www.opencores.org/lgpl.shtml ////\r
-//// ////\r
-//////////////////////////////////////////////////////////////////////\r
-// \r
-// CVS Revision History \r
-// \r
-// $Log: User_int_sim.v,v $\r
-// Revision 1.3 2006/11/17 17:53:07 maverickist\r
-// no message\r
-//\r
-// Revision 1.2 2006/01/19 14:07:50 maverickist\r
-// verification is complete.\r
-//\r
-// Revision 1.2 2005/12/13 12:15:35 Administrator\r
-// no message\r
-//\r
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator\r
-// no message\r
-// \r
-module User_int_sim (\r
- Reset,\r
- Clk_user,\r
- CPU_init_end,\r
-\r
- Rx_mac_ra,\r
- Rx_mac_rd,\r
- Rx_mac_data,\r
- Rx_mac_BE,\r
- Rx_mac_pa,\r
- Rx_mac_sop,\r
- Rx_mac_eop,\r
-\r
- Tx_mac_wa,\r
- Tx_mac_wr,\r
- Tx_mac_data,\r
- Tx_mac_BE,\r
- Tx_mac_sop,\r
- Tx_mac_eop\r
-);\r
-\r
- input Reset;\r
- input Clk_user;\r
- input CPU_init_end;\r
-\r
- input Rx_mac_ra;\r
- output Rx_mac_rd;\r
- input [31:0] Rx_mac_data;\r
- input [1:0] Rx_mac_BE;\r
- input Rx_mac_pa;\r
- input Rx_mac_sop;\r
- input Rx_mac_eop;\r
-\r
- input Tx_mac_wa;\r
- output reg Tx_mac_wr;\r
- output reg [31:0] Tx_mac_data;\r
- output reg [1:0] Tx_mac_BE; // Big endian\r
- output reg Tx_mac_sop;\r
- output reg Tx_mac_eop;\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-// Internal signals\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- reg [4:0] operation;\r
- reg [31:0] data;\r
- reg Rx_mac_rd;\r
- reg Start_tran;\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-//generate Tx user data\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- initial\r
- begin\r
- operation = 0;\r
- data = 0;\r
- end\r
-\r
- task SendPacket;\r
- input [15:0] Length;\r
- input [7:0] StartByte;\r
-\r
- reg [15:0] Counter;\r
- reg [7:0] TxData;\r
-\r
- begin\r
- Counter=Length;\r
- TxData = StartByte;\r
- Tx_mac_sop = 1; // First time\r
- while ( Counter>0 )\r
- begin\r
- while ( !Tx_mac_wa )\r
- begin\r
- Tx_mac_wr = 0;\r
- @( posedge Clk_user );\r
- end\r
-\r
- Tx_mac_data[31:24] = TxData;\r
- Tx_mac_data[23:16] = TxData+1;\r
- Tx_mac_data[15:8] = TxData+2;\r
- Tx_mac_data[ 7:0] = TxData+3;\r
- TxData = TxData+4;\r
- if ( Counter<=4 )\r
- begin\r
- // Indicate how many bytes are valid\r
- if ( Counter==4 )\r
- Tx_mac_BE = 2'b00;\r
- else\r
- Tx_mac_BE = Counter;\r
- Tx_mac_eop = 1;\r
- end\r
- Tx_mac_wr = 1;\r
-\r
- if ( Counter >= 4 )\r
- Counter = Counter - 4;\r
- else\r
- Counter = 0;\r
- @( posedge Clk_user );\r
- Tx_mac_sop = 0;\r
- end\r
-\r
- Tx_mac_eop = 0;\r
- Tx_mac_wr = 0;\r
- Tx_mac_data = 32'h0;\r
- Tx_mac_BE = 2'b00;\r
- end\r
- endtask\r
-\r
- always @( posedge Clk_user or posedge Reset )\r
- if (Reset)\r
- Start_tran <= 0;\r
- else if (Tx_mac_eop && !Tx_mac_wa) \r
- Start_tran <= 0; \r
- else if (Tx_mac_wa)\r
- Start_tran <= 1;\r
-\r
- always @(posedge Clk_user)\r
- if (Tx_mac_wa && CPU_init_end)\r
- /* $ip_32W_gen("../data/config.ini",operation,data); */\r
- ;\r
- else\r
- begin\r
- operation <= 0;\r
- data <= 0;\r
- end\r
-\r
- initial\r
- begin\r
- Tx_mac_sop = 0;\r
- Tx_mac_eop = 0;\r
- Tx_mac_wr = 0;\r
- Tx_mac_data = 32'h0;\r
- Tx_mac_BE = 2'b00;\r
-\r
- #100;\r
- while ( Reset )\r
- @( posedge Clk_user );\r
-\r
- @( posedge Clk_user );\r
-\r
- while ( !CPU_init_end )\r
- @( posedge Clk_user );\r
-\r
- SendPacket( 64, 8'h11 );\r
- repeat( 20 )\r
- @( posedge Clk_user );\r
- SendPacket( 1500, 8'h12 );\r
- \r
- end\r
-\r
-// assign Tx_mac_data = data;\r
-// assign Tx_mac_wr = operation[4];\r
-// assign Tx_mac_sop = operation[3];\r
-// assign Tx_mac_eop = operation[2];\r
-// assign Tx_mac_BE = operation[1:0];\r
-\r
-//////////////////////////////////////////////////////////////////////\r
-//verify Rx user data\r
-//////////////////////////////////////////////////////////////////////\r
-\r
- always @ (posedge Clk_user or posedge Reset)\r
- if (Reset)\r
- Rx_mac_rd <= 0;\r
- else if (Rx_mac_ra)\r
- Rx_mac_rd <= 1;\r
- else\r
- Rx_mac_rd <= 0;\r
-\r
- always @ (posedge Clk_user )\r
- if (Rx_mac_pa) \r
- /* $ip_32W_check( Rx_mac_data,\r
- {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});\r
- */\r
- ;\r
-\r
-endmodule\r
projects / debian / gnuradio / blobdiff