Merge commit 'jabele/wbx_tuning'

[debian/gnuradio] / usrp / host / lib / db_wbxng_adf4350.cc

diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index af4eac573512e2260d283bdd57b70dbaa82d958d..c17e8d670faddaa04f89e8a8415c42a75c606dcc 100644 (file)
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -26,15 +26,15 @@
 #include <db_base_impl.h>
 #include <stdio.h>
 
+#define FREQ_C(freq) uint64_t(freq)
 #define INPUT_REF_FREQ FREQ_C(64e6)
 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define FREQ_C(freq) uint64_t(freq)
 #define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ)                            /* input ref freq with doubler turned on */
 #define MIN_INT_DIV uint16_t(23)                                        /* minimum int divider, prescaler 4/5 only */
 #define MAX_RF_DIV uint8_t(16)                                          /* max rf divider, divides rf output */
 #define MIN_VCO_FREQ FREQ_C(2.2e9)                                      /* minimum vco freq */
 #define MAX_VCO_FREQ FREQ_C(4.4e9)                                      /* minimum vco freq */
-#define MAX_FREQ MAX_VCO_FREQ                                           /* upper bound freq (rf div = 1) */
+#define MAX_FREQ DIV_ROUND(MAX_VCO_FREQ, 1)                                           /* upper bound freq (rf div = 1) */
 #define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV)                    /* calculated lower bound freq */
 
 #define CE_PIN        (1 << 3)
@@ -55,7 +55,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
 
     /* Outputs */
     d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
-    d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
+    d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
 
     /* Initialize the pin levels. */
     _enable(true);
@@ -70,6 +70,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
 
 adf4350::~adf4350()
 {
+    d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
     delete d_regs;
 }
 
@@ -95,9 +96,9 @@ void
 adf4350::_enable(bool enable)
 {
     if (enable){ /* chip enable */
-        d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+        d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
     }else{
-        d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
+        d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
     }
 }
 
@@ -133,6 +134,12 @@ adf4350::_set_freq(freq_t freq)
 {
     /* Set the frequency by setting int, frac, mod, r, div */
     if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
+    int min_int_div = 23;
+    d_regs->d_prescaler = 0;
+    if (freq > FREQ_C(3e9)) {
+        min_int_div = 75;
+        d_regs->d_prescaler = 1;
+    }
     /* Ramp up the RF divider until the VCO is within range. */
     d_regs->d_divider_select = 0;
     while (freq < MIN_VCO_FREQ){
@@ -159,7 +166,7 @@ adf4350::_set_freq(freq_t freq)
             d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
         );
         */
-    }while(d_regs->d_int < MIN_INT_DIV);
+    }while(d_regs->d_int < min_int_div);
     /* calculate the band select so PFD is under 125 KHz */
     d_regs->d_8_bit_band_select_clock_divider_value = \
         INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;