Locking, controllable synthesizer on TX and RX

[debian/gnuradio] / usrp / host / lib / db_wbxng_adf4350.cc

diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index 6e74bf0c1014bf189949b3939c504715d3155108..1facfd8828b8267cf5c25a6a6d948c3634246bea 100644 (file)
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -13,11 +13,12 @@
 //#include "io.h"
 //#include "spi.h"
 
-#define INPUT_REF_FREQ FREQ_C(32e6)
+#define INPUT_REF_FREQ FREQ_C(64e6)
 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
+//#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
+#define FREQ_C(freq) uint64_t(freq)
 #define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ)                            /* input ref freq with doubler turned on */
-#define MIN_INT_DIV uint16_t(300)                                        /* minimum int divider, prescaler 4/5 only */
+#define MIN_INT_DIV uint16_t(23)                                        /* minimum int divider, prescaler 4/5 only */
 #define MAX_RF_DIV uint8_t(16)                                          /* max rf divider, divides rf output */
 #define MIN_VCO_FREQ FREQ_C(2.2e9)                                      /* minimum vco freq */
 #define MAX_VCO_FREQ FREQ_C(4.4e9)                                      /* minimum vco freq */
@@ -41,7 +42,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
 
     /* Outputs */
     d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
-    d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
+    d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
 
        /* Initialize the pin levels. */
        _enable(true);
@@ -104,7 +105,14 @@ adf4350::_write(uint8_t addr, uint32_t data){
     s[3] = (char)(data & 0xff);
     std::string str(s, 4);
 
+    timespec t;
+    t.tv_sec = 0;
+    t.tv_nsec = 5e6;
+
+    nanosleep(&t, NULL);
     d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
+    nanosleep(&t, NULL);
+
     fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
        /* pulse latch */
     //d_usrp->write_io(d_which, 1, LE_PIN);
@@ -122,7 +130,8 @@ adf4350::_set_freq(freq_t freq){
                d_regs->d_divider_select++; //double the divider
        }
        /* Ramp up the R divider until the N divider is at least the minimum. */
-       d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+       //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+       d_regs->d_10_bit_r_counter = 2;
        uint64_t n_mod;
        do{
                d_regs->d_10_bit_r_counter++;
@@ -141,7 +150,14 @@ adf4350::_set_freq(freq_t freq){
        }while(d_regs->d_int < MIN_INT_DIV);
        /* calculate the band select so PFD is under 125 KHz */
        d_regs->d_8_bit_band_select_clock_divider_value = \
-               INPUT_REF_FREQ/(FREQ_C(125e3)*d_regs->d_10_bit_r_counter) + 1;
+               INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+    fprintf(stderr, "Band Selection: Div %u, Freq %lu\n", 
+        d_regs->d_8_bit_band_select_clock_divider_value, 
+               INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+    );
+       d_regs->_load_register(5);
+       d_regs->_load_register(3);
+       d_regs->_load_register(1);
        /* load involved registers */
        d_regs->_load_register(2);
        d_regs->_load_register(4);