// Tx and Rx have shared defs, but different i/o regs
#define ENABLE_5 (1 << 7) // enables 5.0V power supply
#define ENABLE_33 (1 << 6) // enables 3.3V supply
-#define RX_TXN (1 << 5) // Tx only: T/R antenna switch for TX/RX port
-#define RX2_RX1N (1 << 5) // Rx only: antenna switch between RX2 and TX/RX port
+//#define RX_TXN (1 << 15) // Tx only: T/R antenna switch for TX/RX port
+//#define RX2_RX1N (1 << 15) // Rx only: antenna switch between RX2 and TX/RX port
+#define RX_TXN ((1 << 5)|(1 << 15)) // Tx only: T/R antenna switch for TX/RX port
+#define RX2_RX1N ((1 << 5)|(1 << 15)) // Rx only: antenna switch between RX2 and TX/RX port
#define RXBB_EN (1 << 4)
#define TXMOD_EN (1 << 4)
#define PLL_CE (1 << 3)
t.tv_nsec = 10000000;
nanosleep(&t, NULL);
- fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
- int_freq, freq_result, d_common->_get_locked());
+ //fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
+ // int_freq, freq_result, d_common->_get_locked());
// FIXME
// Offsetting the LO helps get the Tx carrier leakage out of the way.
//set_lo_offset(4e6);
// Disable VCO/PLL
- d_common->_enable(false);
+ d_common->_enable(true);
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
}
if(on) {
v = TXMOD_EN;
// Enable VCO/PLL
- d_common->_enable(true);
+ //d_common->_enable(true);
}
else {
v = RX_TXN;
// Disable VCO/PLL
- d_common->_enable(false);
+ //d_common->_enable(false);
}
return usrp()->write_io(d_which, v, mask);
}
float
wbxng_base_tx::gain_min()
{
- return usrp()->pga_max();
+ return 0.0;
}
float
wbxng_base_tx::gain_max()
{
- return usrp()->pga_max() + 25.0;
+ return 25.0;
}
float
wbxng_base_tx::gain_db_per_step()
{
- return 1;
+ return gain_max()/(1+(1.4-0.5)*4096/3.3);
}
bool
float pga_gain, agc_gain;
float V_maxgain, V_mingain, V_fullscale, dac_value;
- float maxgain = gain_max() - usrp()->pga_max();
+ float maxgain = gain_max();
float mingain = gain_min();
- if(gain > maxgain) {
- pga_gain = gain-maxgain;
- assert(pga_gain <= usrp()->pga_max());
- agc_gain = maxgain;
- }
- else {
- pga_gain = 0;
- agc_gain = gain;
- }
+ pga_gain = 0;
+ agc_gain = gain;
- V_maxgain = 0.7;
+ V_maxgain = 0.5;
V_mingain = 1.4;
V_fullscale = 3.3;
dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
- fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
+ //fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
assert(dac_value>=0 && dac_value<4096);
return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
- && _set_pga(int(pga_gain)));
+ && _set_pga(usrp()->pga_max()));
+
}
usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
usrp()->write_io(d_which, (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
- fprintf(stderr,"Setting WBXNG RXBB on");
+ //fprintf(stderr,"Setting WBXNG RXBB on");
// set up for RX on TX/RX port
select_rx_antenna("TX/RX");
d_is_shutdown = true;
// do whatever there is to do to shutdown
- // Power down
- usrp()->common_write_io(C_RX, d_which, power_off(), (ENABLE_33|ENABLE_5));
-
// Power down VCO/PLL
d_common->_enable(false);
// fprintf(stderr, "wbxng_base_rx::shutdown before set_auto_tr\n");
set_auto_tr(false);
+ // Power down
+ usrp()->write_io(d_which, power_off(), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+
// fprintf(stderr, "wbxng_base_rx::shutdown after set_auto_tr\n");
}
}
{
int attn_code = int(floor(attn/0.5));
unsigned int iobits = (~attn_code) << ATTN_SHIFT;
- fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
+ //fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
return usrp()->write_io(d_which, iobits, ATTN_MASK);
}