# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
# Pin & Location Assignments
# ==========================
set_global_assignment -name TOP_LEVEL_ENTITY usrp_std
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
# Fitter Assignments
# ==================
# ========================
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP Off
+set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
- set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
# end CLOCK(SCLK)
# ---------------
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
- set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
# end CLOCK(master_clk)
# ---------------------
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
- set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
# end CLOCK(usbclk)
# -----------------
# Timing Assignments
# ==================
- set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
- set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
- set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
# end ENTITY(usrp_std)
# --------------------
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE usrp_std.vh
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v